C
C. Auth
Researcher at Intel
Publications - 28
Citations - 5036
C. Auth is an academic researcher from Intel. The author has contributed to research in topics: PMOS logic & NMOS logic. The author has an hindex of 16, co-authored 28 publications receiving 4815 citations.
Papers
More filters
Proceedings ArticleDOI
A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging
Kaizad Mistry,C. Allen,C. Auth,B. Beattie,Daniel B. Bergstrom,M. Bost,M. Brazier,M. Buehler,Annalisa Cappellani,R. Chau,C. H. Choi,G. Ding,K. Fischer,Tahir Ghani,R. Grover,W. Han,D. Hanken,M. Hattendorf,J. He,J. Hicks,R. Huessner,D. Ingerly,Pulkit Jain,R. James,L. Jong,Subhash M. Joshi,C. Kenyon,K. Kuhn,K. Lee,Huichu Liu,J. Maiz,B. Mclntyre,P. Moon,J. Neirynck,S. Pae,C. Parker,D. Parsons,Chetan Prasad,L. Pipes,M. Prince,Pushkar Ranade,T. Reynolds,J. Sandford,Lucian Shifren,J. Sebastian,J. Seiple,D. Simon,Swaminathan Sivakumar,Pete Smith,C. Thomas,T. Troeger,P. Vandervoorn,S. Williams,K. Zawadzki +53 more
TL;DR: In this paper, a 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process, resulting in the highest drive currents yet reported for NMOS and PMOS.
Proceedings ArticleDOI
A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors
Tahir Ghani,Mark Armstrong,C. Auth,M. Bost,P. Charvat,G. Glass,T. Hoffmann,K. Johnson,C. Kenyon,Jason Klaus,B. McIntyre,Kaizad Mistry,Anand Portland Murthy,J. Sandford,M. Silberstein,Swaminathan Sivakumar,Pete Smith,K. Zawadzki,Scott E. Thompson,M. Bohr +19 more
TL;DR: In this article, the authors describe a novel strained transistor architecture which is incorporated into a 90nm logic technology on 300mm wafers, which features an epitaxially grown strained SiGe film embedded in the source drain regions.
Journal ArticleDOI
A 90-nm logic technology featuring strained-silicon
Scott E. Thompson,Mark Armstrong,C. Auth,Mohsen Alavi,M. Buehler,R. Chau,S. Cea,Tahir Ghani,G. Glass,T. Hoffman,Chia-Hong Jan,C. Kenyon,Jason Klaus,K. Kuhn,Z. Ma,B. McIntyre,Kaizad Mistry,Anand Portland Murthy,B. Obradovic,Ramune Nagisetty,P. Nguyen,Swaminathan Sivakumar,R. Shaheed,Lucian Shifren,B. Tufts,S. Tyagi,M. Bohr,Y. El-Mansy +27 more
TL;DR: In this paper, a leading-edge 90-nm technology with 1.2-nm physical gate oxide, 45-nm gate length, strained silicon, NiSi, seven layers of Cu interconnects, and low/spl kappa/CDO for high-performance dense logic is presented.
Proceedings ArticleDOI
A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors
C. Auth,C. Allen,A. Blattner,Daniel B. Bergstrom,Mark R. Brazier,M. Bost,M. Buehler,V. Chikarmane,Tahir Ghani,Timothy E. Glassman,R. Grover,W. Han,D. Hanken,Michael L. Hattendorf,P. Hentges,R. Heussner,J. Hicks,D. Ingerly,Pulkit Jain,S. Jaloviar,Robert James,David Jones,J. Jopling,Subhash M. Joshi,C. Kenyon,Huichu Liu,R. McFadden,B. McIntyre,J. Neirynck,C. Parker,L. Pipes,Ian R. Post,S. Pradhan,M. Prince,S. Ramey,T. Reynolds,J. Roesler,J. Sandford,J. Seiple,Pete Smith,Christopher D. Thomas,D. Towner,T. Troeger,Cory E. Weber,P. Yashar,K. Zawadzki,Kaizad Mistry +46 more
TL;DR: In this paper, a 22nm generation logic technology is described incorporating fully-depleted tri-gate transistors for the first time, which provides steep sub-threshold slopes (∼70mV/dec) and very low DIBL ( ∼50m V/V).
Journal ArticleDOI
A logic nanotechnology featuring strained-silicon
Scott E. Thompson,Mark Armstrong,C. Auth,S. Cea,R. Chau,G. Glass,T. Hoffman,Jason Klaus,Z. Ma,B. McIntyre,Anand Portland Murthy,B. Obradovic,Lucian Shifren,Swaminathan Sivakumar,S. Tyagi,Tahir Ghani,Kaizad Mistry,Mark T. Bohr,Y. El-Mansy +18 more
TL;DR: In this article, a tensile Si nitride-capping layer is used to introduce tensile uniaxial strain into the n-type MOSFET and enhance electron mobility.