Proceedings ArticleDOI
Impact of remnant stress/strain and metal contamination in 3D-LSIs with through-Si vias fabricated by wafer thinning and bonding
M. Murugesan,J.C. Bea,Hisashi Kino,Yuki Ohara,Toshiya Kojima,Akihiro Noriki,Kang-Wook Lee,K. Kiyoyama,Takafumi Fukushima,Hiroshi Nohira,Takeo Hattori,Eiji Ikenaga,Tetsu Tanaka,Mitsumasa Koyanagi +13 more
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TLDR
In this paper, the impact of mechanical stress and metal contamination in the thinned Si substrate has been investigated by micro-Raman spectroscopy (µRS) and XPS.Abstract:
Wafer thinning and formation of through-Si via (TSV) and metal microbump are key processes in 3D LSI fabrication. However, it might introduce mechanical stress and crystal defects in thinned wafers. In addition, Cu for TSV and microbump might introduce metal contamination in thinned Si substrate. Then the impact of mechanical stress and metal contamination in the thinned Si substrate has been investigated. The remnant stress left after wafer thinning was evaluated by micro-Raman spectroscopy (µRS) and XPS. It was found that the mechanical stress remained in the back surface of Si substrate after wafer thinning and a part of this mechanical stress appeared in the surface of Si substrate. The metal contamination in such thinned Si substrate has been evaluated by a C-t method. It was found that the carrier generation lifetime was degraded by Cu diffused into Si substrate at relatively low temperature of 200 °C. The mechanical stress/strain in the thinned Si substrate after wafer bonding was also evaluated to investigate the influences of metal microbumps to the thinned Si substrate. It was found that the local mechanical stress was generated in the Si substrate surface by the microbumps. This local stress caused a 3% change in the ON current of MOS transistor.read more
Citations
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Journal ArticleDOI
Multichip-to-Wafer Three-Dimensional Integration Technology Using Chip Self-Assembly With Excimer Lamp Irradiation
Takafumi Fukushima,E. Iwata,Yoshikazu Ohara,M. Murugesan,Jichoel Bea,Kang-Wook Lee,Tetsu Tanaka,Mitsumasa Koyanagi +7 more
TL;DR: In this paper, a flip-chip self-assembly with metal microbump electrodes is used to increase the stacking throughput/yield and chip alignment accuracy of conventional chip-to-wafer 3D integration.
Proceedings ArticleDOI
3D integration technology and reliability
TL;DR: In this article, reliability issues in these 3D LSIs such as mechanical stresses induced by through-silicon vias and metal microbumps and Cu contamination in thinned wafers are discussed.
Proceedings ArticleDOI
Impact of Cu diffusion from Cu through-silicon via (TSV) on device reliability in 3-D LSIs evaluated by transient capacitance measurement
TL;DR: In this paper, the influence of Cu contamination from Cu through-silicon via (TSV) on device reliability in the 3D LSI was electrically evaluated by capacitance-time (C-t) measurement.
Journal ArticleDOI
Technology Assessment of Through-Silicon Via by Using $C$ – $V$ and $C$ – $t$ Measurements
G. Katti,Michele Stucchi,Dimitrios Velenis,Sarasvathi Thangaraju,K. De Meyer,Wim Dehaene,Eric Beyne +6 more
TL;DR: In this paper, C-V characteristics of through-silicon vias were compared to demonstrate the reproducibility of the TSV process module in terms of the minimum TSV depletion capacitance in the operating voltage region.
Proceedings ArticleDOI
Highly beneficial organic liner with extremely low Thermal stress for fine Cu-TSV in 3D-integration
M. Murugesan,Takafumi Fukushima,Jichoel Bea,Yutaka S. Sato,Hideki Hashimoto,Kang-Wook Lee,Mitsumasa Koyanagi +6 more
TL;DR: In this paper, the constructive role played by the thermal-chemical vapor deposited (CVD) organic polyimide (PI) liner in the Cu-TSVs with diameter or width (φ) varying from 3 µm to 30 µm has been studied meticulously for its thermal stability, leakage current (LC), capacitance, TSV-chain resistance, stress absorbing ability, and the Si-lattice distortion arising from thermo-mechanical stress (TMS).
References
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Journal ArticleDOI
High-Density Through Silicon Vias for 3-D LSIs
TL;DR: The 3-D microprocessor test chip,3-D memorytest chip, 3- D image sensor chip, and 3-Ds artificial retina chip were successfully fabricated by using poly-Si TSV and tungsten (W/poly-Si) TSV technology.
High-Density Through Silicon Vias for 3-D LSIs : Silicon stacked chips that perform highly-parallel data transfer have been successfully fabricated for image processing, artificial retinas, and for microprocessor and memory testing
TL;DR: In this paper, a polycrystalline silicon (poly-Si) TSV technology and tungsten (W)/poly poly-Si TSV for 3D integration was developed.
Journal ArticleDOI
Three-Dimensional Integration Technology Based on Wafer Bonding With Vertical Buried Interconnections
Mitsumasa Koyanagi,T. Nakamura,Yusuke Yamada,H. Kikuchi,Takafumi Fukushima,Tetsu Tanaka,Hiroyuki Kurino +6 more
TL;DR: In this article, a 3D shared-memory test chip with three-stacked layers was fabricated by bonding the wafers with vertical buried interconnections after thinning.
Journal ArticleDOI
New Three-Dimensional Wafer Bonding Technology Using the Adhesive Injection Method.
T. Matsumoto,Masakazu Satoh,Katsuyuki Sakuma,Hiroyuki Kurino,Nobuaki Miyakawa,H. Itani,Mitsumasa Koyanagi +6 more
TL;DR: In this paper, a new 3D wafer bonding technology using the adhesive injection method has been proposed, in order to realize a real-time micro-vision system and a real shared memory.
Journal ArticleDOI
Tungsten Through-Silicon Via Technology for Three-Dimensional LSIs
Hirokazu Kikuchi,Yusuke Yamada,Atif Mossad Ali,Jun Liang,Takafumi Fukushima,Tetsu Tanaka,Mitsumasa Koyanagi +6 more
TL;DR: In this article, the Tungsten through-silicon via (W-TSV) technology is investigated for the fabrication of three-dimensional (3D) LSI chips having low resistive TSVs with a width less than 3 µm.