V
V. Kamakoti
Researcher at Indian Institute of Technology Madras
Publications - 124
Citations - 992
V. Kamakoti is an academic researcher from Indian Institute of Technology Madras. The author has contributed to research in topics: Field-programmable gate array & Benchmark (computing). The author has an hindex of 17, co-authored 121 publications receiving 901 citations. Previous affiliations of V. Kamakoti include National Institute of Technology, Tiruchirappalli & Indian Institute of Science.
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Proceedings ArticleDOI
Impact of Temperature on Test Quality
TL;DR: A viable low-cost alternative to temperature testing that quantifies the impact of temperature variations on the test quality and also determines optimal test conditions is proposed and shows that majority of the defects that were originally detected by temperature-testing are also detected by the proposed test flow.
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A buffer-sizing algorithm for network-on-chips with multiple voltage-frequency Islands
TL;DR: A two-phase algorithm to size the switch buffers in network-on-chips (NoCs) considering support for multiple-frequency islands is proposed, which results in 42% reduction in amount of buffering when compared to a standard buffering approach.
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An Accuracy Tunable Non-Boolean Co-Processor Using Coupled Nano-Oscillators
TL;DR: This article uses a two coupled nano-oscillator as a basic computational model and proposes an architecture for a non-Boolean coupled oscillator based co-processor capable of executing certain functions that are commonly used across a variety of approximate application domains, including an accuracy tunable knob.
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Temporal Redundancy Based Encoding Technique for Peak Power and Delay Reduction of On-Chip Buses
TL;DR: A new temporal encoding scheme is proposed, which uses self-shielding memory-less codes to completely eliminate worst-case crosstalk effects and hence significantly minimizes power consumption and delay of the bus.
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Memmap: technology mapping algorithm for area reduction in FPGAs with embedded memory arrays using reconvergence analysis
TL;DR: This paper presents a methodology to utilize such unused EMBs as large look-up tables to map multi-output combinational sub-circuits of the application, which, otherwise would be mapped on to a number of small look-ups available on the FPGA.