Showing papers in "African Review of Physics in 2009"

Electronic and optical properties of rare-earth chalcogenides and pnictides

Abstract: The dielectric description of crystal ionicity deve loped by Phillips and Van Vechten has been successfully employed in a wide range of semi-conductors and insulators. However, the applicability of this Phillips and Van Vech ten (P.V.V) dielectric analysis has been limited to only simple A N B 8-N compounds. An empirical relationship previously in troduced by the authors, relating the electronic properties of zinc blende a nd complex structured solids to their product of io nic charges, is shown to be applicable with minor modifications to the rock salt structured solids. An alternative approach to the well-known P.V.V. theory has been evolved in order to understand the electronic and optical properties such as heteropol ar gap (E c), average energy gap (E g), crystal ionicity (f i) and optical dielectric constants ( e∞) of REX (RE = rare earth metals, X = S, Se, Te, P, As and Sb). The estimation is based on the approximate inverse relationship between the electronic pro perties and the product of ionic charges of these compounds. The evaluated values are in better agreement with the mod ified P.V.V. theory.

Enhancement of Dielectric Constant in Metal-Dielectric Meta-materials

Abstract: A two component meta-material as copper cylindrical wires embedded periodically in the host dielectric material (wax) is studied with a viewpoint of measuring and analys ing its electric and magnetic properties in the fre quency range from 0.5 to 5 GHz. A large enhancement of the effective diel ectric constant relative to the dielectric constant of the matrix material is observed in the considered periodic metal-dielectri c structures. The increase of enhancement of the ef fective dielectric constant with the increase of wires diameter is als o observed. A method for measuring the effective di electric and magnetic constants of meta-materials is also presented brief ly to compare it with the results obtained by numer ical simulations in the considered frequency range. An analysis of both mea surement and simulation results is carried out. A c omparison of such analysis with the appropriative analysis of similar meta-material structures with magnetic metal (iron ) wires conducted in the earlier work is also presented.

THE EFFECT OF SHORT CHANNEL ON NANOSCALE SOI MOSFETs

Abstract: Double gate silicon-on-insulator (DG SOI) devices have recently been of great interest, particularly for the investigation of sub-10nm field-effect transistor [1]-[3]. As the channel length is reduced from one transistor generation to the next, the susceptibility of the transistor to short-channel effects (SCE) is monitored in several ways such as threshold voltage (VTH) roll-off, sub-threshold voltage swing, and the drain induced barrier low, the channel length decreases and becomes crucial in deep-submicrometer technologies. As an indicator of these short channel effects, the threshold voltage and sub-threshold voltage swing has been extensively investigated [4]-[7]. In order to maintain a tolerable degree of short channel effect [8], it becomes necessary to reduce the SOI film thickness. Reducing the SOI film thickness causes a high electric field in the perpendicular direction to the Si/SiO2 interface, strongly confining charge carriers in the channel. Several interesting models have been proposed for the classical (i.e., without quantum effects) drain current [9]-[11]. Carrier quantization effects have been considered for the first time in [12]. Therefore, classical models that disregard these effects are no longer suitable for describing sub 10nm MOSFETs. Therefore, we use quantum mechanical transport models for n-channel MOSFETs based on the self-consistent Schrodinger and Poisson equations for the simulation of short channel effects on the performance of DGMOSFET. In addition to it, the model is continuous over all gate and drain bias ranges, which makes it very suitable to simulate novel silicon transistor structures. 2. Results

Full and reduced-order synchronization of chaos in josephson junction

Abstract: In this paper, the synchronization between two diff erent Josephson junction models is investigated bas ed on variable back-stepping technique. Firstly, we examined the s ynchronization of identical RCL-shunted Josephson junction (RCLSJ) systems emanating from different initial conditions by means of a proposed variable back-stepping tech nique. Secondly, by utilizing a reduced-order synchronization technique , we realized synchronization between the third ord er RCLSJ model and the parametrically modulated Josephson junction (PMJJ) system (second order). In both cases, the desi gned controllers are singular in nature and thus easier to construct and implement in practice. They ensure that the state s of the controlled chaotic slave system exponentially synchronize with the sta te of the master system. Numerical simulations are illustrated to verify the proposed methods.

F2 region response to the magnetic storm of january 10, 1976 at american sector

Abstract: This paper attempts to study the F2 region response to an intense (Dst = -158nT) geomagnetic storm of January 10, 1976 using the critical frequency foF2 and using the data obtained from ionosonde stations in the American sector of the world. The stations were classified into high, middle and low latitudes, respectively. To analyze the behaviour of the F2 region, we employed the parameter D(foF2), which is the normalized deviation of the critical frequency foF2 from the reference. From our analysis, it was observed that (i) there is an absence of the positive ionospheric storm effects at high and mid latitudes on the dayside during the initial phase of the storm, (ii) there is a simultaneous existence of the negative storm at the high and the middle latitudes, and (iii) there is an occurrence of strong positive phase at the low latitude station. However, this observed simultaneous depletion of foF2 at high and middle latitudes revealed that the depletion of the F2 region plasma density is due to changes in the neutral wind produced predominantly by the Joule heating in the aurora zone. Hence the F2 region response during the magnetic activity of January 10, 1976 at the American sector of the world lacked simultaneity as the depression does not extend to low latitude.

Characterization of the Short Channel Effect on the Threshold Voltage in Deep Sub-micron MOSFETs

Abstract: The importance of new physical and electrical pheno mena was not realized in recent past, but it turned out to be essential today to extract some essential parameters and to s imulate the statics and dynamics of advanced transi stor technologies. Various phenomena such as the quantification of the silicon substrate, the depletion of the gate on po ly-silicon and the increasing importance of the parasitic effects, kno wn as extrinsic, influence the MOSFETs conventional behavior. Currently, these effects start to play a major role and are ab out to become dominating because of the strong incr ease in the levels of doping, the reduction thicknesses of oxide gate and the channel length. Neglecting these parasitic effects could be the cau se of unacceptable errors, which could be due to th eir involvement in significant variations and the prediction-measureme nts for many key sizes of any design, such as the t hreshold voltage (Vth), the trans-conductance (gm, gds), the charge injecti on (Qij), the trans-capacities (Cij). Various approaches to modeling and extraction coexist in order to model the threshold voltage. The app lication of mathematical model is exploited for the extraction of characteristic length (LLC) [1]. The extraction of the threshold voltage for any MOSFETs with many channel lengths and the extraction of characteristic length with the variati on of threshold voltage (Vth) are shown in Fig. 1. The threshold voltage (Vth) is reduced, on the one hand by the reduction in channel length and the thi ckness of oxide gate (in the case of High K one uses equivalent thi ckness EOT) and on the other hand, by the effect of the drain induced barrier lowing (DIBL) and substrate voltage. The alg orithm for extraction characteristic length (Lc) is based on the equation of the tangent at low values of channel length.

On Silicon On Insulator Technology and Devices

Abstract: This article describes the silicon on insulator tec hnologies (SOI) and devices. Different methods of f orming SOI wafers are presented and advantages and weakness of the massive silicon technology is reviewed. SOI-MOSFET related physical and electrical phenomena, as well as some innovating architectures is presented. 1. Presentation of SOI technologies Massive silicon is the material on which microelectronics is based. In the MOS technology carried out on massive silicon, only a finite part close to the interface is used for electrical conduction and the remainder is without utility. On the other hand, in SOI technologies a silicon film is carried by a more or less thick insulating layer under which the silicon wafer is located. The SOI material is thus only one stacking of three layers as shown in Fig. 1.

Design Choices for Folded Cascode Operational Trans-conductance Amplifiers

Abstract: The operational amplifier, op-amp, is without question the most common building block in analog systems Among many architectures, the Operational Trans-conductance Amplifiers OTAs, the structure known as "Folded Cascode OTA" (Fig1) has found a broad use [1,2,3], because of its reduced thermal noise and a possible optimization of power consumption [4] Although, at first glance, the calculation of elements of this structure seems to be straightforward and raises no apparent problem, choices of input transistors type (N-OTA or P-OTA configuration), currents ratios and the Overdrive Voltage Vov are left to the designer appreciation and did not obey well established criteria The purpose of our study is on the one hand, to provide directives on the tradeoffs to be made to arrive at the desired performances and on the other hand, to establish the limitations of the studied structure

Coaxial probe fixture used for complex permittivity measurements of thin layers

Abstract: The use of new materials in recent times constitute s an alternative to solve some of the problems of e lectronics. A good knowledge of the parameters of electrical is needed . For these reasons, we have developed a broad-band technique for measuring the complex relative permittivity ( e*) of dielectric materials, especially the thin lay ers. Our method is based on the use of a coaxial probe ending to a trough. The extraction of the complex permittivity uses a capac itance model associated with metal losses correction. There is several adva ntages which result from this approach such as meas urement simplicity. The dielectric is directly placed in the slit with its short dimensions which naturally reduces the im pact of the metal. The same is true for the lithography. This method cover s easily the bandwidth between 0.5 and 11 GHz according to the dimensions considered.

A Simple FPGA-Based Lossless Wireless Transmitter/Receiver Using the Residue Number System

Abstract: Wireless system design often feature FPGAs alongside DSPs and FPGAs, which offer superior speed compared to other processors and operate close to the antenna and are the core of a larger processor in the transmitter and receiver blocks. In the transmitter, a methodology to analyze factored orthogonal 1-D DWT based on the wavelet lifting scheme and the RNS is used. The wavelet lifting scheme is used because it allows an in-place implementation and reduces the forward transform to a sequence of simple steps involving elementary algebraic operations that make it trivial to find the inverse transform [1, 2]. However, scaling is inherent in all lifting transforms and does not yield integer results. Many methods exist to overcome this scaling [3]. However, these approaches introduce further processing that can increase algorithmic complexity. To simplify system design, the scaling factor is assumed to be unity in this approach. As a result, minimization of the circuit design is enhanced while retaining system high-fidelity. The residue digits from the RNS and wavelet lifting scheme are transformed into orthogonal signals through the mapping to a set of Walsh functions. The orthogonal signals are then multiplexed unto a carrier wave and transmitted to the receiver. In the receiver, the low-pass equivalent composite signal made-up of the set of orthogonal signals is passed through a bank of correlators. The scalar products of the transmitted signal and stored copies of the Walsh functions are used to find the optimum estimate of the residue digits. The Chinese remainder theorem is later used to recover the message. In the proposed communication system, the message is considered to be subjected only to quantization noise. The channel requirements and the FPGA inherent speed render effects due to additive white Gaussian noise negligible. It is shown that [4], for a quantization error, Pe ≤ 10 the decoding errors have negligible effect. Using this error threshold, the RMS error for different moduli set is calculated for a given test signal.

A STUDY OF INTENSE MAGNETIC STORMS DEVELOPMENT (USING Dst SIGNATURE) AND ITS ASSOCIATION WITH MAGNETIC CLOUDS

Abstract: This paper attempts to study the development of intense magnetic storms using storm time Dst index and its association with magnetic clouds. For the purpose of this work, we have selected eight rather strong geomagnetic storms occurred in different seasons in 1976-2002. The Dst index is used in relation to other interplanetary and geomagnetic parameters because changes in the large-scale electric fields in the solar wind during intense geomagnetic storms can be reproduced from the variation in Dst value. It was observed that over 70% of the storm events under investigation are generated from magnetic clouds which are characterized by low beta plasma, high Interplanetary Magnetic Field (IMF) magnitude and large scale coherent field rotations often including large and steady north-south components. It was also shown that the storm events having peak Dst < -250nT are more prone to having magnetic clouds as their main source of generation than others. However, this class of storms takes a longer time to recover after its main phase than those between the range -250nT ≤ peak Dst < -100nT with respect to their Dst plots.

Adaptive acquisition of pn sequence in nonfading awgn channel

Abstract: In this paper, we consider an adaptive single dwell serial search system of pseudo-noise (PN) sequence s for direct sequences spread-spectrum (DS-SS) systems in no fading additive white Gaussian noise channels. Since the received signal levels in mobile communications are unknown and location varying, the acquisition schemes for pseudo-n oise (PN) sequences with fixed thresholds may cause too many false alarms. Therefore, adaptively varying thresh old schemes are proposed through the use of a constant false alarm rate (CFAR) algorithm. From the simulation results, w e observe that the DS/CDMA systems with CFAR processor outperforms the conventional scheme with fixed threshold.

Recent Trends in IGBT Technology

Abstract: MOS devices have very fast switching speed and require very low gate current drive. However, MOSFET are majority carrier devices and so their on-resistance drastically increases with DrainSource voltage rating, restricting their exploitation to voltages less than a few hundred volts. On the other hand, bipolar transistors have good on-state characteristics but long switching times, especially at turn off. They are current controlled devices with small current gains, which require complex base-drive circuits to provide the base current during on-state, which increases power losses in the control electrode. The IGBT is a hybrid device obtained by the integration of a BJT and a MOSFET in a Darlington configuration. The IGBT allows a great reduction of conduction losses even for high voltage rating (low on-state resistance), low power gate drive losses (insulated grid) and it can switch today in of less than 100 ns, whereas only 3 μs about 20 years ago. In addition, the current density of IGBT is 20 times larger as compared to MOSFET and 5 times as compared to BJT. The IGBT is, basically, a horizontal channel and vertical current MOSFET cell (VDMOS), except for the N+ Drain layer, which is substituted by a P+ layer at the collector.

Tungsten trioxide nanoplates prepared without organics at low temperature

Abstract: *Tungsten trioxide (WO 3) nanoplates have been synthesized successfully by a simple reaction of tungsten powder and water without any organics at 300 o C. The formation of nanoplates by the reaction of m etals with water is suggested to occur due of decomposition of water by the metal giving h ydrogen. The nanoplates are having an average thick ness of 150nm and an average width of 400nm. A feasible mechanism for the formation of nanoplates has been discussed in view of the experimental results. Compared with other methods, t he present method is fast, economical, low temperat ure, and free of pollution which will make it suitable for large sca le production. Moreover, the technique does not req uire any sophisticated equipments and as such can be extended and expanded to other oxides. To our knowledge, the technique h as not been reported in the literature earlier.

I-V Characterization for a Deeper Comprehension of Buried Double Junction Color Detector Behavior

Abstract: CMOS sensors still use photodiodes and RGB optical filters combination This method entails many limitations to the color imaging sensor performances In fact, the use of three photo-sites per image pixel augments the sensor surface and its cost Further, the additional technology process needed to deposit optical filters decreases pixel sensitivities and increases the Fixed Pattern Noise (FPN) We reported that buried junctions color detectors [1] give good alternatives to overcome these limitations and improve color sensor performances By using the optical properties of silicon, each active area of these detectors gives the color information without use of optical filters By its two photocurrents, the Buried Double pn Junction (BDJ) detector gives both wavelength and optical power of a monochromatic light This allows the use of the BDJ device for accurate multispectral cameras and astronomical imaging system development Furthermore, the device can be implemented in a standard CMOS technology [1] and then benefits from the advancements in Active Pixel Sensor (APS) architectures However, CMOS image sensors may suffer from dark current level, which is the main parameter that determines image sensor performances By lowering this parameter, device sensitivity and signal to noise ratio will be enhanced Furthermore, the dark current level has a non-negligible contribution to the sensor Fixed Pattern Noise (FPN) The present work focuses on the BDJ color detector dark current and studies its voltage and temperature dependencies For this purpose, a reliable model of the BDJ dark current is proposed The approach we used takes into account different physical phenomena such as carrier diffusion from the quasi-neutral regions, thermal generationrecombination occurring in the depletion layers and tunneling mechanisms [2-5] It also consists of experimental extraction of device’s physical and electrical parameters To validate the accuracy of the model, measurements of the reverse I-V characteristics were carried out and compared to simulation results Good agreement is obtained between simulations and measurements The two junctions show different behaviors We found that tunneling effect is the dominant mechanism for the shallow junction dark current, while for the deep junction thermal Shockley-Read-Hall generation is the main mechanism The theoretical discussion has been confirmed by the temperature dependence of the BDJ detector dark current measurements and by device simulations Indeed, to distinguish the different mechanisms that contribute to the BDJ dark current, measurements of the I-V characteristics at different temperatures ranging from 40 °C to 60 °C were carried out Knowing the BDJ dark current mechanisms and the temperature dependence, we are able to analyze and understand the dark current behavior of the various BDJ Active Pixel Sensor architectures

MOBILITY EXTRACTION IN UNIAXIALLY AND BIAXIALLY STRAINED N-MOSFETs

Abstract: Strained-Si technology is of great interest since it allows enhanced carrier mobility which in its turn increases drive current [1]. However, it is not clear whether the mobility gain of strained Si nMOSFETs is due to the gain in conduction mass [2,3] or to reduced phonon scattering rate [4]. In this paper, we present a detailed parameter extraction method for the analysis of mobility between the process induced (uniaxial) and the substrate induced (biaxial) strained nMOSFETs.

A Bi-facial Silicon Solar Cell Parameters Determination by Impedance Spectroscopy

Abstract: In this paper, a bi-facial silicon solar cell under white light illumination and under the application of constant magnetic field is studied in frequency modulation. To determine parameters such as series resistance, parallel resistance and capacitance, we utilized the Nyquist diagram by plotting the imaginary versus real part of the solar cell impedance. The use of the Bode diagram p ermits us to extract the minority carrier lifetime. Thus, all electric and electronic parameters depend on the ap plied magnetic field.

Electrochemical deposition of nickel thin films onto monocristalline silicon

Abstract: Thin magnetic films deposited directly onto silicon enable the linkage of silicon technology with magnetic properties. Magnetic thin films are a promising material in the developing technology of high density storage devices. The possibility of metal deposition directly on silicon opens up the opportunities of signal processing in a single device [1, 2]. Metallic films are generally produced by physical methods such as PVD, CVD and others. An old technique such as electro-deposition appears as a new alternative to obtain deposited films with some advantages: room temperature deposition, relative simplicity and low cost. The electro-deposition of metals directly on n-type silicon without a seed layer is possible when the silicon is sufficiently conductive to allow electrodeposition directly onto it. Electro-deposition on a semiconductor is quite different from that on metal. When a semiconductor electrode is introduced in an electrolyte, a space charge layer is formed in the semiconductor. In a metal electrode, this space charge is so thin that it can be neglected because of the high donor density. On a semiconductor electrode, an applied potential does not drop only in a double layer at the solid – liquid interface as on metals, it also drops along the space charge layer in the solid [3, 4]. In the present work, we present results concerning the electrochemical conditions suitable for plating Ni thin films onto n-Si (100). The energy levels of the interface n-Si (100)/Ni were determined from MottSchottky plots. The deposits were prepared at various current densities from sulphate bath containing metallic ions and boric acid. An aspect related to the deposition process was investigated by cyclic voltammetry. The film structure and morphology were examined by X-rays diffraction and scanning electron microscopy. Typically, thin compact metallic films were obtained. The electro-deposition of metals onto semiconductors is strongly dependent on the relative position of the equilibrium potential of the redox couple in the solution with respect to the flat band potential of the semiconductor [4,5,6]. In this work, the flat band potential and the donor density were determined from the Mott-Schottky plot (Fig.1) for n-Si in the sulphate bath. A flat band potential of -0.68 V was obtained. From the slope (2/eND e e0), the donor density of 3.9 x 10 14 was calculated. The volammograms for the gold (Au) electrode in the sulphate bath and for n-Si electrode in the same bath are shown in Fig. 2. It can be seen that the reduction potential of Ni on Au electrode begin at -0,55V (point A), whereas on the Si electrode, it begin at -0.94 V (point B).

Design and hardware implementation of embedded controller devices

Abstract: The goal of this work is to implement a PI controller on FPGA device using RTL Processor architecture composed of specific Finite State Machine associated with the custom Data-path (FSMD). In this project, we are interested in the current loop controller with a variable speed DC motor control. However, in order to generalize this study to any other system, control can be done easily using the same steps discussed in the following sections. We present at the beginning, a brief presentation of the DC control loops, and we describe the digitalization of the control algorithm in order to obtain an easy and efficient implementation. From this description and according to the FPGA design flow, we deduce the dataflow graph (DFG) behavioural description of the current PI controller. Then, we discuss two FSMD architectures with timing and surface optimization. After that, we present the implementation results of these architectures. Finally, we present the used Co-simulation model for the validation of the FPGA PI current components in the cascade control loop.

Theoretical Investigation and Computation of Time Dependent CW NMR Blood-flow Signal for the Estimation of Blood Flow Parameters

Abstract: V and the blood vessel cross-section. Starting with the time dependent Bloch equations, we have generated an equation that prese nts a CW NMR blood signal, whose profile corresponds to the human cardiac cycle. Using a spin-spin relaxation time o f 0.1 s, blood steady velocity of 20 cm/s (typical of a healthy human) and a peak pulse velocity of 30 cm/s, our model provides results very close to those obtained by conventiona l NMR pulse machines and other modality like the Ultrasound Doppler (US) technique. The application of our CW NMR model technique for the determination of blood flow parameters of i mportance covers a wide range of variations seen in human patients.

MODELLING AND CHARACTERIZATION OF GaAs MESFET

Abstract: The development of low noise amplifiers and receivers for communication components that can operate also at high frequencies and present decreasing geometric sizes, the field effect transistors are the solution The FETs modeling is one of the preoccupations of certain researchers to understand some phenomenon of this component Our work consists essentially of improving the implementation of an analytical model called PHS (Pucel, Hauss and statz) This model allows us to describe the variation of the basic elements of the equivalent schema in small signal with the gate and drain voltage using different simplified hypotheses To produce the characteristics evolution, we need introduce the first region’s length For this, we have brought a personnel idea based on the discretization of the channel and establish a test to define the channel’s pinching To validate the model we performed a simulation which permitted us to obtain the principal functional characteristics of the MESFET as the variation of the drain currant versus the drain voltage for several values of the gate voltage We notice that, the current is linear with the drain source voltage until the saturation value, where it becomes steady So we have two areas: linear and saturation We obtained the current’s maximum for null value of the gate source voltage

Rtos evolution and hardware microkernel implementation benefits

Abstract: Due to the importance and complexity of real-time a pplications, the demands on real-time platforms inc rease every year, which motivates moving these applications onto multiprocessor hardware system on chip (MPSoC). This paper deals with different methods used for efficient handling of re al time design projects leading to their successful completion, not just completion on time, but completion with as little s ilicon surface as possible. In the following pages, we outline the evolution of Real Time Operating System (RTOS) architecture and their limitations, compare different approaches an d investigate the gain using the hardware implementation with microkernel structure for these RTOS that will improve bot h performance and design time.

An Ad-hoc IP Functional Verification Procedure

Abstract: This paper presents an ad-hoc IP-verification proce dure that is used to verify the conformity between the IP specifications and their corresponding HDL-code implementation. The verification procedure is a genera l purpose solution offering an automatic validation to any IP design. The purpose of this paper is to provide a full desc ription of the verification procedure and how to tailor it in order to fit any particular needs. The Ad-hoc verification procedure has been used to validate several designed IPs, notably: FIFO, Trans ceiver and I 2 C-salve. The whole procedure code is implemented in both Verilog 2001 (IEEE 1365) and VHDL (2002).