Showing papers in "Microprocessors and Microsystems in 2003"

TL;DR: It is hoped that this implementation and fixed-point error analysis will lead to a better understanding of the issues involved in finite register length implementation of the discrete fractional Fourier transform and will help the signal processing community make better use of the transform.

TL;DR: It is demonstrated how the removal of the clock secures a potential point of attack and enables additional fine-grain timing countermeasures to be introduced in smart card functions that are resistant to both side-channel and fault injection attacks.

TL;DR: The Least Laxity First (LLF) scheme outperforms the Fixed Priority Preemptive (FPP), Earliest Deadline First (EDF), and Guaranteed Percentage (GP) schemes, but suffers from the highest implementation costs.

TL;DR: This paper illustrates how standard component-based middleware can be enhanced to flexibly compose static QoS provisioning policies with application logic, adaptive middleware capabilities enable developers to abstract and encapsulate reusable dynamic QoS Provisioning and adaptive behaviors, and component- based middleware and adaptivemiddleware capabilities can be integrated to provide a total QoS procurement solution for DRE applications.

TL;DR: Software implemented error-injection tests show that the smoothing voter achieves a compromise between the result selection capabilities of the median voter and the safety features of the majority voter, and is an appropriate voter for applications in which maximising the number of correct outputs and minimising the numbers of benign errors of the system is the main concern.

TL;DR: A CAD system is presented that builds a bridge between CAs as models of physical systems and processes, andCAs as a VLSI architecture, and simulations of the operation of these VLSi systems showed that the corresponding CA has been successfully implemented into hardware.

TL;DR: This paper presents the practical implementation of a system, with two emitters and four receivers, using a low-cost hardware architecture based on a FPGA, and the ultrasonic signal processing is performed in real time.

TL;DR: A new temporal partitioning methodology used for the data-path part of an algorithm for the reconfigurable embedded system design that uses the dynamic reconfiguration in order to minimize the number of cells needed to implement theData-path of an application under a time constraint.

TL;DR: An electronic system for telemetry and control applications of distributed systems consists of a portable electronic circuit that can be connected up to various types of sensors depending on the application to be used in each case, together with a mobile-telephony communications system.

TL;DR: Coll collaborative techniques for multimedia streaming, scheduling and pre-fetching embedded in the QoS middleware architecture for dynamic group management of heterogeneous computing devices and an underlying QoS-provisioning mechanism to support not only heterogeneous clients, but also dynamic configuration change of them.

TL;DR: Both theoretical analysis and measurements, taken from running these procedures on a four-processor computer platform, indicate that the procedure of the linear array architecture presents the best speed-up ratio.

TL;DR: Three methods of time measurement are described, including a method of testing set-up and hold times, using uncorrelated signals with known statistics, and selecting the conditions to be tested on-chip.

TL;DR: Initial analyses indicate that the secure SPA achieved up to 80% improvement in resistance against non-invasive attacks albeit at the cost of reduced performance and increased area and power consumption.

TL;DR: An approach and framework for addressing the problem of identifying an appropriate and valid set of timing requirements in order that the best use can be made of the advances in scheduling theory by the use of modelling techniques that allow for emergent properties such as timing behaviour.

TL;DR: A synchronous mode as well as a scan mode of operation are added to a large class of asynchronous circuits, in compliance with LSSD design rules, which enables the application of mainstream tools for design-for-testability and test-pattern generation to asynchronous circuits.

TL;DR: The paper claims that the provision of services with negotiated and controlled QoS over best-effort networks is achievable via distributed support infrastructures that activate some of the nodes along the network path between clients and servers.

TL;DR: The designs propagate a timing pulse along with the data values, and the logic elements have delays that decrease in the presence of the pulse, which produces a surfing effect wherein events are bound in close proximity to the timing pulse.

TL;DR: This work addresses the issue of FC bandwidth and FC optimization, i.e. how many and which credits to return per packet cycle, and introduces the concepts of credit contention and credit scheduling.

TL;DR: This paper will tackle the very complex and challenging issue to develop a comprehensive architecture to allow mobile wireless user to acces MPEG-4 flows while moving and at a given level of QoS.

TL;DR: This paper describes a method of generating test sequences from a Modechart specification using symbolic execution technique and demonstrates, using the railroad crossing system, how to construct a time-annotated symbolic execution tree and generate test sequences according to the selected coverage criteria.

TL;DR: This paper summarizes the earlier architectures and presents the new concepts for DAQ, and substitutes rack-mounting backplane buses for high speed point-to-point links, abandoned centralized event building, and instead use switched networks and parallel architectures.

TL;DR: A systematic method is proposed that is simple, rigorous and general for determining the absolute lower bound of packet buffering required by practical switching systems and its usefulness is demonstrated by dimensioning the internal buffer capacity of two popular CIOQ switches.

TL;DR: A 12- inch wafer prealigner that can recognize optical characters on a 12-inch wafer and generate smooth velocity command profiles for motors is proposed and developed.

TL;DR: This approach provides a thin, transparent layer on top of existing environments that can be easily installed for all active applications, and solves the heterogeneity within the active networks.

TL;DR: This work focuses on the description of a real-time correlation assessment procedure applied to electrocardiogram signals, which can be applied to design compact ECG monitoring systems consisting on a system on chip where programmable logic offloads the main processor.

TL;DR: It is shown that usage of this D 2 -CPU (Data-Driven) processor, follows the natural flow of programs, minimizes redundant (micro)operations, lowers the hardware cost, and reduces the power consumption.

TL;DR: This work developed a parallel STAP algorithm on an IBM SP2 parallel computing system and on ADSP 21062 Dual-DSP system, which executes efficiently on digital signal processor (DSP)-based systems.

TL;DR: The experimental results show that the proposed framework improves the performance of e-commerce transactions while providing a high quality of security services for desired e- commerce transactions.

TL;DR: This work proposes a scheme in which each synchronous module has both an incoming and an outgoing clock signal, which have been obtained by opening the module's ring oscillator, and demonstrates the technique in the context of processors and memories.

TL;DR: The design is based on modelling the energy equation of Hopfield neural network to a systolic (or modular) form and it is shown mathematically that the modified energy equation converges in all circumstances.