Proceedings ArticleDOI
1.1 Computing's energy problem (and what we can do about it)
Mark Horowitz
- pp 10-14
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TLDR
If the drive for performance and the end of voltage scaling have made power, and not the number of transistors, the principal factor limiting further improvements in computing performance, a new wave of innovative and efficient computing devices will be created.Abstract:
Our challenge is clear: The drive for performance and the end of voltage scaling have made power, and not the number of transistors, the principal factor limiting further improvements in computing performance. Continuing to scale compute performance will require the creation and effective use of new specialized compute engines, and will require the participation of application experts to be successful. If we play our cards right, and develop the tools that allow our customers to become part of the design process, we will create a new wave of innovative and efficient computing devices.read more
Citations
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Journal ArticleDOI
On the Design of Logarithmic Multiplier Using Radix-4 Booth Encoding
Ratko Pilipovic,Patricio Bulić +1 more
TL;DR: An energy-efficient approximate multiplier which combines radix-4 Booth encoding and logarithmic product approximation and a datapath pruning technique is proposed and studied to reduce the hardware complexity of the multiplier.
Proceedings ArticleDOI
Stream-based memory access specialization for general purpose processors
Zhengrong Wang,Tony Nowatzki +1 more
TL;DR: This work proposes ISA-extensions for decoupled-streams, which interact with the core using a FIFO-based interface that can enable: prefetch stream accesses to hide memory latency, semi- binding decoupling access to remove address computation and optimize the memory interface, and finally inform cache policies.
Journal ArticleDOI
An Always-On 3.8 $\mu$ J/86% CIFAR-10 Mixed-Signal Binary CNN Processor With All Memory on Chip in 28-nm CMOS
TL;DR: A mixed-signal binary convolutional neural network (CNN) processor for always-on inference applications that achieves 3.8 mW per classification, an improvement over the previous low-energy benchmark on CIFAR-10, achieved in part by sacrificing some programmability.
Journal ArticleDOI
Opto-electronic memristors: Prospects and challenges in neuromorphic computing
Alexandros Emboras,Alessandro Alabastri,Paul Lehmann,Kevin Portner,Christoph Weilenmann,Ping Ma,Bojun Cheng,Mila Lewerenz,Elias Passerini,Ueli Koch,Jan Aeschlimann,Fabian Ducry,Juerg Leuthold,Mathieu Luisier +13 more
TL;DR: This Perspective paper introduces a class of electro-optical memristors that can emulate the key properties of synapses and neurons, which are essential features for the realization of electro -optical neuromorphic functionalities.
Proceedings ArticleDOI
AdderSR: Towards Energy Efficient Image Super-Resolution
TL;DR: Hu et al. as mentioned in this paper proposed to use adder neural networks (AdderNets) to calculate the output features to avoid massive energy consumptions of conventional multiplications for image super-resolution.
References
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Design of ion-implanted MOSFET's with very small physical dimensions
TL;DR: This paper considers the design, fabrication, and characterization of very small Mosfet switching devices suitable for digital integrated circuits, using dimensions of the order of 1 /spl mu/.
Book
Low Power Digital CMOS Design
TL;DR: The Hierarchy of Limits of Power J.D. Stratakos, et al., and Low Power Programmable Computation coauthored with M.B. Srivastava, provide a review of the main approaches to Voltage Scaling Approaches.
IEEE International Solid-State Circuits Conference
Hurwitz Jonathan Ephraim David,Stewart Smith,A. A. Murray,Peter B. Denyer,John Thomson,Scot D. Anderson,E. Duncan,B. Paisley,A. Kinsey,E. Christison,B. Laffoley,J. Vittu,R. Bechignac,Robert Henderson,M.J. Panaghiston,P.-F. Pugibet,H. Hendry,K. M. Findlater +17 more
Journal ArticleDOI
Towards energy-proportional datacenter memory with mobile DRAM
Malladi Krishna T,Benjamin C. Lee,Frank Austin Nothaft,Christos Kozyrakis,Karthika Periyathambi,Mark Horowitz +5 more
TL;DR: This work architects server memory systems using mobile DRAM devices, trading peak bandwidth for lower energy consumption per bit and more efficient idle modes, and demonstrates 3-5× lower memory power, better proportionality, and negligible performance penalties for data-center workloads.