Proceedings ArticleDOI
1.1 Computing's energy problem (and what we can do about it)
Mark Horowitz
- pp 10-14
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TLDR
If the drive for performance and the end of voltage scaling have made power, and not the number of transistors, the principal factor limiting further improvements in computing performance, a new wave of innovative and efficient computing devices will be created.Abstract:
Our challenge is clear: The drive for performance and the end of voltage scaling have made power, and not the number of transistors, the principal factor limiting further improvements in computing performance. Continuing to scale compute performance will require the creation and effective use of new specialized compute engines, and will require the participation of application experts to be successful. If we play our cards right, and develop the tools that allow our customers to become part of the design process, we will create a new wave of innovative and efficient computing devices.read more
Citations
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Journal ArticleDOI
Through-Silicon Vias: Drivers, Performance, and Innovations
TL;DR: This paper reviews TSVs with focus on the following: key drivers for TSV-based integration; TSV fabrication techniques; 3) TSV electrical and thermomechanical performance fundamentals and characterization techniques; and 4) novel technologies to attain enhanced performance beyond the state-of-the-art TSVs.
Posted Content
Morph: Flexible Acceleration for 3D CNN-based Video Understanding
TL;DR: A novel accelerator called "Morph" is designed, that can adaptively support different spatial and temporal tiling strategies depending on the needs of each layer of each target 3D CNN, the core kernel in modern video understanding.
Proceedings ArticleDOI
DRC 2 : Dynamically Reconfigurable Computing Circuit based on memory architecture
Kaya Can Akyel,Henri-Pierre Charles,Julien Mottin,Bastien Giraud,Gregory Suraci,Sebastien Thuries,Jean-Philippe Noel +6 more
TL;DR: A novel energy-efficient and Dynamically Reconfigurable Computing Circuit (DRC2) concept based on memory architecture for data-intensive and secure applications and can perform extremely-parallel operations enabling the processing of large volume of data is presented.
Proceedings ArticleDOI
Agile SoC development with open ESP
Paolo Mantovani,Davide Giri,Giuseppe Di Guglielmo,Luca Piccolboni,Joseph Zuckerman,Emilio G. Cota,Michele Petracca,Christian Pilato,Luca P. Carloni +8 more
TL;DR: ESP as discussed by the authors is an open-source research platform for heterogeneous SoC design, which combines a modular tile-based architecture with a variety of application-oriented flows for the design and optimization of accelerators.
Journal ArticleDOI
Deep In-Memory Architectures in SRAM: An Analog Approach to Approximate Computing
TL;DR: DIMA’s computational pipeline is described and a Shannon-inspired rationale for its robustness to process, temperature, and voltage variations and design guidelines to manage its analog nonidealities are provided and the fundamental tradeoff between energy and accuracy in the low-compute SNR regime is analyzed to determine energy-optimum design parameters.
References
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Design of ion-implanted MOSFET's with very small physical dimensions
TL;DR: This paper considers the design, fabrication, and characterization of very small Mosfet switching devices suitable for digital integrated circuits, using dimensions of the order of 1 /spl mu/.
Book
Low Power Digital CMOS Design
TL;DR: The Hierarchy of Limits of Power J.D. Stratakos, et al., and Low Power Programmable Computation coauthored with M.B. Srivastava, provide a review of the main approaches to Voltage Scaling Approaches.
IEEE International Solid-State Circuits Conference
Hurwitz Jonathan Ephraim David,Stewart Smith,A. A. Murray,Peter B. Denyer,John Thomson,Scot D. Anderson,E. Duncan,B. Paisley,A. Kinsey,E. Christison,B. Laffoley,J. Vittu,R. Bechignac,Robert Henderson,M.J. Panaghiston,P.-F. Pugibet,H. Hendry,K. M. Findlater +17 more
Journal ArticleDOI
Towards energy-proportional datacenter memory with mobile DRAM
Malladi Krishna T,Benjamin C. Lee,Frank Austin Nothaft,Christos Kozyrakis,Karthika Periyathambi,Mark Horowitz +5 more
TL;DR: This work architects server memory systems using mobile DRAM devices, trading peak bandwidth for lower energy consumption per bit and more efficient idle modes, and demonstrates 3-5× lower memory power, better proportionality, and negligible performance penalties for data-center workloads.