ETH Library
99.1% Efficient 10 kV SiC-Based
Medium-Voltage ZVS Bidirectional
Single-Phase PFC AC/DC Stage
Journal Article
Author(s):
Rothmund, Daniel ; Guillod, Thomas ; Bortis, Dominik ; Kolar, Johann W.
Publication date:
2019-06
Permanent link:
https://doi.org/10.3929/ethz-b-000342563
Rights / license:
In Copyright - Non-Commercial Use Permitted
Originally published in:
IEEE Journal of Emerging and Selected Topics in Power Electronics 7(2), https://doi.org/10.1109/JESTPE.2018.2886140
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For more information, please consult the Terms of use.
1
99.1 % Efficient 10 kV SiC-Based Medium Voltage
ZVS Bidirectional Single-Phase PFC AC/DC Stage
Daniel Rothmund, Student Member, IEEE, Thomas Guillod, Student Member, IEEE,
Dominik Bortis, Member, IEEE and Johann W. Kolar, Fellow, IEEE
Power Electronic Systems Laboratory, ETH Zurich, 8092 Zurich, Switzerland;
email: rothmund@lem.ee.ethz.ch
Abstract—Due to their extremely high energy demand, data
centers are directly supplied from a medium voltage (MV) grid.
However, a significant part of this energy is dissipated in the
power supply chain, since the MV is reduced step-by-step through
multiple power conversion stages down to the chip voltage level.
In order to increase the efficiency of the power supply chain,
the number of conversion stages must be substantially reduced.
In this context, Solid-State Transformers (SSTs) are considered
as a possible solution as they could directly interface the MV
AC grid to a 400 V DC bus, whereby server racks with a
power consumption of several tens of kilowatts could be directly
supplied from an individual SST. With a focus on the lowest
system complexity, the SST ideally should be built as simple
two-stage system consisting of an MV AC/DC PFC rectifier
stage followed by an isolated DC/DC converter. Accordingly,
this paper focuses on the design and realization of a 25 kW,
3.8 kV single-phase AC to 7 kV DC PFC rectifier unit based on
10 kV SiC MOSFETs. By simply adding an LC-circuit between
the switch nodes of the well-known full-bridge-based PWM
AC/DC rectifier, the integrated Triangular Current Mode (iTCM)
concept is implemented, which only internally superimposes a
large triangular current ripple on the AC mains current and
therefore enables zero voltage switching (ZVS) over the entire
AC mains period. Special attention is paid to the realization of
the MV inductors and their electrical insulation, the AC-input
LCL-filter to limit EMI emissions, and the challenges arising due
to cable resonances when connecting the SST to the MV grid
via a MV cable. Despite the large insulation distances required
for MV, the realized 25 kW MV PFC rectifier achieves an
unprecedented power density of 3.28 kW/L (54 W/in
3
) and
a full-load efficiency of 99.1 %, determined using a calorimetric
measurement setup, which is discussed in detail in the Appendix.
Index Terms—Medium-voltage, AC/DC, soft-switching, ZVS,
10 kV SiC MOSFETs, calorimetric measurement.
I. INTRODUCTION
One of today’s largest and fastest growing energy consumers
is the information and communication technology (ICT) sec-
tor, which currently consumes 10 % of the world’s generated
electric energy [1]. Especially the continuous processing and
provisioning of data by data centers is highly energy demand-
ing. E.g. in 2014, the 14 million installed servers in the U.S.
consumed 1.8 % of the national electric energy generation
[2]. Furthermore, it is reported that 12 . . . 27 % of the energy
provided to data centers at medium voltage (MV) level is
dissipated in the power conversion stages which convert the
voltage from several kilovolts down to the chip voltage level
[3]–[5]. Therefore, for economical and ecological reasons, the
L
f
u
g
AC
DC
DC
DC
AC
DC
DC
DC
AC
DC
DC
DC
U
DC,LV
(a)
AC
DC
DC
DC
U
DC,LV
L
g
C
f
R
d
L
f
u
g
(b)
P = 25 kWu
g
= 3.8 kV rms
U
DC,LV
= 400 V
u
ML
Fig. 1: (a) Multi-cell and (b) single-cell realization of a MV AC to 400 V
DC SST.
interest of research institutions and industry on more efficient
data center power supplies has grown rapidly over the past
decade. In order to increase the efficiency and to reduce the
complexity (and therewith the probability of failure) of the
conventional multi-stage power supply chain of data centers,
a shift to a 380/400 V DC distribution system is considered
[4] and partly already implemented [6]. As a next step, Solid-
State Transformer (SST) technology is considered to provide
a direct power electronic interface from the MV AC grid to
400 V DC, in order to improve the efficiency and the power
density also of this part of the conversion chain [5], [7],
[8]. Thereby, the power supply of each server rack (which
can reach power demands in the range of 20 . . . 40 kW, [3],
[9], [10]) with a separate SST is intended. In this case, the
power could be distributed on MV level (e.g. 6.6 kV phase-to-
phase rms, i.e. 3.8 kV rms phase-to-neutral) with the advantage
of substantially lower realization efforts and/or cable cross
sections and lower ohmic losses compared to low-voltage(LV)
distribution. Individual single-phase SSTs (single-phase for a
low complexity) could then convert the MV into 400 V DC
and feed individual server racks or clusters, whereby the three
phases of the MV utility grid could be symmetrically loaded.
For a cost-effective construction of the building, it would be
important that the SSTs are compact and lightweight. For the
This is the author's version of an article that has been published in this journal. Changes were made to this version by the publisher prior to publication.
The final version of record is available at http://dx.doi.org/10.1109/JESTPE.2018.2886140
Copyright (c) 2019 IEEE. Personal use is permitted. For any other purposes, permission must be obtained from the IEEE by emailing pubs-permissions@ieee.org.
2
sake of completeness, it should be mentioned that this kind of
SST would also be well suited for high power battery charging
in transportation applications [11], [12] and for the integration
of renewable energy, e.g. photovoltaic power plants, into the
MV grid [13].
Up to now, interfaces to the MV grid are typically
built as multi-cell converters with an input-series output-
parallel connection of multiple converter cells e.g. based on
1200 V . . . 1700 V SiC MOSFETs, i.e. wide bandgap devices
with the highest blocking voltages commercially available at
the moment. Thereby, the individual converter cells consist of
a PFC AC/DC converter stage and a series-connected isolated
DC/DC stage, as shown in Fig. 1(a). In order to minimize
the boost inductance, the AC/DC converters can be operated
with phase-shifted carriers, resulting in a switched multi-level
AC voltage u
ML
, which closely follows the MV grid voltage
u
g
, and therefore leads to a small input current ripple. Such
a system with a total power of 25 kW has been presented
by industry in [14] and achieves a full-load efficiency of
96 % from 2.4 kV AC to 54 V DC. Even though multi-cell
converters can achieve a high conversion performance, they
are also highly complex due to the high number of switches,
gate drivers, isolated auxiliary supplies, and voltage/current
measurements.
As an alternative, with the new generation of 10 kV SiC
MOSFETs, it is possible to interface the MV grid directly with
a single-cell converter, consisting of a single-cell AC/DC PFC
rectifier followed by an isolated single-cell DC/DC converter,
as shown in Fig. 1(b). The EMI noise injected into the MV
grid is then limited by an additional LCL-filter in front of
the PFC rectifier, which is a typical filter structure used for
MV converters [15]. Due to the greatly reduced complexity
compared to the multi-cell approach, a higher reliability and
higher power density is expected. In order to prove this
statement and to explore the limits in efficiency and power
density of the single-cell approach, a bidirectional 25 kW,
3.8 kV AC to 400 V DC SST with an intermediate 7 kV DC-
link is realized, where the focus of this paper is on the AC/DC
converter stage, the LCL-filter, and the challenges arising from
interfacing the SST to the MV grid via a MV cable, which
could be subject to undesired oscillations that need to be
avoided by a termination network.
Due to the high blocking voltage of the utilized 10 kV SiC
MOSFETs, a simple full-bridge-based PWM AC/DC converter
topology is chosen. However, without further measures, hard-
switching and thus high switching losses would occur [16]–
[20]. Consequently, the achievable efficiency and power den-
sity would be strongly restricted, since the switching losses
define an upper limit for the switching frequency, and hence
inhibit a possible downsizing of passive components. The
most effective strategy to reduce the switching losses is to
apply soft-switching techniques and to profit from the typically
much lower soft-switching losses compared to hard-switching.
Additionally, EMI can be significantly reduced with soft-
switching, since the du/dt values are typically much lower
than for hard-switching.
Soft-switching can be achieved e.g. with the Triangular
Current Mode (TCM) concept [21]–[24], where the boost
inductance value is reduced to such extent, that the large
high-frequency (HF) triangular current ripple superimposed
to the instantaneous low-frequency (LF) grid current leads
to a reversal of the current direction in the semiconductors
in each switching cycle and accordingly enables zero-voltage
switching (ZVS) for each switching transition, resulting in
extremely low switching losses compared to hard-switching.
On the other hand, however, with the TCM operation the
boost inductor design becomes more challenging since both,
the HF and the LF current, are flowing through the same
inductor. In order to keep the HF losses in the inductor low,
the employment of HF litz wire with thin strand diameter and
HF core materials (e.g. ferrite) is necessary. Unfortunately, litz
wire features a low copper filling factor and also the saturation
flux density of HF core materials is typically low. However,
in order to keep also the LF losses low, a winding with a
high copper filling factor (i.e. solid copper wire) and a core
material with a high saturation flux density (e.g. amorphous
iron, iron powder or nanocrystalline core material) would be
needed. Hence, with TCM operation, a reasonable trade-off
between HF and LF losses has to be found in the design of
the boost inductor.
In order to overcome this disadvantage, the concept of
the integrated Triangular Current Mode (iTCM) operation is
utilized for the realization of the considered 25 kW, 3.8 kV
single-phase AC to 7 kV DC converter [25], [26]. By adding an
LC-circuit between the switch nodes of the full-bridge PWM
AC/DC converter, the TCM current can be split into HF and
LF current components, which are then flowing through two
separate inductors, cf. Fig. 2(a). A similar concept has been
presented in [27] for high power density 400 V DC/DC ap-
plications. Advantageously, the large TCM ripple current then
does not flow towards the grid (as usual for TCM topologies)
but is kept internally in the circuit. Accordingly, this concept
is called integrated Triangular Current Mode (iTCM). Since
the superposition of HF and LF current, i.e. the TCM current,
is only needed in the semiconductor devices to guarantee soft-
switching, this current separation enables a dedicated design of
the two inductors, i.e either optimized for LF or HF currents,
and thus results in an expected efficiency improvement. A
further advantage of the iTCM concept is, that the well-
known PWM modulation scheme still can be applied and no
additional control or measurement circuitry, e.g. current zero
crossing detection as needed in TCM operation, is required.
This paper is organized as follows: Section II gives a brief
overview over the iTCM converter topology and its modula-
tion. In Section III, the design procedure of the individual
components of the converter is presented. Special attention is
paid to the design of MV inductors and their insulation, as well
as the connection of the SST to the MV grid without exciting
oscillations in the supplying MV cable. Section IV shows
the experimental setup together with the experimental results,
including waveforms and the calorimetrically measured con-
verter efficiency and loss distribution. Finally, conclusions are
drawn in Section V and a detailed explanation and error
analysis of the applied calorimetric efficiency measurement
methods is given in the Appendix.
This is the author's version of an article that has been published in this journal. Changes were made to this version by the publisher prior to publication.
The final version of record is available at http://dx.doi.org/10.1109/JESTPE.2018.2886140
Copyright (c) 2019 IEEE. Personal use is permitted. For any other purposes, permission must be obtained from the IEEE by emailing pubs-permissions@ieee.org.
3
II. THE INTEGRATED TRIANGULAR CURRENT MODE
(iTCM) CONCEPT
The iTCM converter topology consists of a MOSFET full-
bridge, an LCL-filter and the aforementioned LC-branch as
shown in Fig. 2(a). In order to not expose the AC-source
(which could be e.g. a secondary winding of a MV trans-
former) to HF common mode (CM) voltages, the bridge
leg {S
21
, S
22
} is operated as unfolder with mains frequency,
i.e. 50/60 Hz, whereas the bridge leg {S
11
, S
12
} is PWM
modulated. However, the iTCM concept would also work
in case both bridge legs would be PWM modulated. The
corresponding duty cycles d
HF
and d
LF
of the HF and the
LF bridge legs, respectively, are shown in Fig. 2(c). Besides
the mains input current i
Lg
flowing through L
g
, the LC-branch
consisting of C
b
and L
b
now draws a triangular (inductive)
HF current i
b
, such that the sum of these currents i
A
, which
flows out of the switch node A, changes its sign during each
switching cycle, enabling soft-switching as shown in Fig. 2(b).
Thereby, the task of the capacitor C
b
is to block any LF AC
current flow through L
b
. The boost inductor L
g
is dimensioned
in such a way, that it carries only a small current ripple
∆i
Lg,pp
, while the current ripple in L
b
has to be chosen
such that i
A
reaches a negative value of at least −I
ZVS
in the
corresponding switching transitions, in order to guarantee soft-
switching over the whole mains period. Thereby, the current
I
ZVS
is the desired turn-off current of the HF bridge leg
which can be calculated based on the effective output charge
Q
OSS
of the switching devices required to charge/discharge the
output capacitances C
OSS
of the power MOSFETs (and further
parasitic capacitances), and the maximum allowed duration of
this resonant switching transition (i.e. the dead time duration
T
dt
), which also defines the minimum and maximum duty
cycles of the converter [24]. Hence, in order not to limit the
duty cycle range and/or to be able to control the input/output
voltage in a wide range, T
dt
has to be small, e.g. k = 1 % of
the switching period T
p
. The minimum required current I
ZVS
can roughly be calculated as
I
ZVS
= Q
OSS
/T
dt
= Q
OSS
/ (k · T
p
) . (1)
The critical point, where the highest current in L
b
is needed,
is located at the peak of the mains current. The inductance
values of L
b
and L
g
can be dimensioned in such a way
that a turn-off current of −I
ZVS
is achieved in this operating
point. However, the goal is to achieve a constant ZVS current
over the whole mains period to reduce the rms current in the
LC-branch and the MOSFETs, which is not possible when
the switching frequency is kept constant [25]. Therefore, the
switching frequency has to be varied within the mains period,
whereby a minimum switching frequency f
min
is defined at
the peak of the mains current and is set to f
min
= 35 kHz
for the converter at hand (cf. Fig. 2(d)). With the known
minimum switching frequency and the purpose of achieving
a turn-off current of −I
ZVS
at the peak of the mains current,
the inductance of L
b
can be calculated as a function of the
peak-to-peak current ripple r (in % of the peak mains current)
10 kV SiC
L
g
U
DC
L
b
C
b
C
f
R
d
L
f
u
g
i
g
i
Lg
i
b
i
A
u
SN
C
DC
(a)
S
11
S
12
S
21
S
22
Current
0
-I
ZVS
S
11
S
12
S
21
S
22
Time
T
1
0
T
p
+T
1
2T
p
T
p
(b)
i
g,LF
i
b
i
b
= 0
i
g
= i
Lg
i
A
i
Lg
Δi
Lg,pp
i
f
A
B
u
AB
Current [A]
-20
-10
0
10
20
I
ZVS
i
b
i
Lg
i
b,env+
i
g,env-
I
ZVS
i
b,env-
(e)
Time [ms]
0
5
10 15 20
20
0
40
60
f
sw
[kHz]
f
min
80
0
0.5
1
Duty-Cycle
d
HF
d
LF
f
sw
(c)
(d)
Fig. 2: (a) Circuit diagram of the MV PFC rectifier with AC-side LCL-
filter and additonal LC-branch consisting of L
b
and C
b
to implement the
integrated TCM operation, which enables soft-switching over the entire AC
mains period. (b) Detailed view of the inductor current waveforms i
b
and
i
Lg
together with the current i
A
= i
b
+ i
Lg
flowing out of the HF bridge
leg {S
11
, S
12
}. (c) Duty cycles d
HF
and d
LF
of the HF and LF bridge legs.
(d) Variable switching frequency f
sw
required to guarantee a constant ZVS
current. (e) Envelopes of the currents i
b
and i
Lg
over a mains period.
in the boost inductor L
g
as
L
b
=
ˆu
2
g
2P (2 − r) + 2I
ZVS
ˆu
g
1 −
ˆu
g
U
DC
1
f
min
, (2)
whereby ˆu
g
denotes the peak AC grid voltage (ˆu
g
=
√
2 ·u
g
),
U
DC
denotes the DC-link voltage, and P denotes the system
power. Furthermore, the inductance of the boost inductor L
g
,
dimensioned for a maximum current ripple r, can be found as
L
g
=
ˆu
2
g
2rf
min
P
1 −
ˆu
g
U
DC
. (3)
The condition of a constant ZVS current I
ZVS
can be visual-
ized e.g. during the positive half-cycle of the mains period as
This is the author's version of an article that has been published in this journal. Changes were made to this version by the publisher prior to publication.
The final version of record is available at http://dx.doi.org/10.1109/JESTPE.2018.2886140
Copyright (c) 2019 IEEE. Personal use is permitted. For any other purposes, permission must be obtained from the IEEE by emailing pubs-permissions@ieee.org.
4
the difference of the upper envelope i
b,env+
of the current
in L
b
and the lower envelope i
g,env−
of the current in
L
g
, as shown in Fig. 2(e) (if an offset-free current i
b
is
assumed, i.e. i
b,env+
= −i
b,env−
). The function to describe
the variable switching frequency to achieve a constant ZVS
current (derived in more detail in [25]) can be found as
f
sw
=
A (t) ˆu
2
g
4P |sin (ω
g
t)| + 2ˆu
g
I
ZVS
·
1
L
g
+
1
L
b
, (4)
whereby
A (t) = |sin (ω
g
t)| ·
1 −
ˆu
g
U
DC
· |sin (ω
g
t)|
. (5)
However, this function holds only for an LF current which
is in phase with the grid voltage (i.e. a pure sine current in
this case). Due to the capacitors C
b
and C
f
(as well as C
t
which will be introduced in Section III-G), the converter has
to deliver a small amount of reactive power, i.e. small LF
cosine currents are superimposed on the inductor currents i
b
and i
Lg
. In order to still maintain a constant ZVS current, this
deviation from the ideal waveforms has to be compensated by
the switching frequency,
f
sw
=
1
L
g
+
1
L
b
·
A (t) ˆu
2
g
4P |sin (ω
g
t)| + 2
ˆu
g
I
ZVS
+ ˆu
2
g
ω
g
C
equ
· cos (ω
g
t)
,
(6)
whereby C
equ
= C
b
+ C
f
is the equivalent capacitance
causing the LF cosine current. Fig. 3 shows the simulated
current waveforms for a peak-to-peak ripple of r = 40 %
in L
g
together with the adapted switching frequency pattern,
whereby the capacitors C
b
and C
f
are taken into account. As
can be seen, the LF current i
f,50 Hz
causes a slight phase-shift
between the grid current i
g
and the boost inductor current i
Lg
.
Nevertheless, with the adapted switching frequency pattern,
the turn-off current I
ZVS
can be kept constant, as can be seen
in the envelope of the current i
A
= i
b
+ i
Lg
flowing out of
the HF bridge leg.
It should be noted that the maximum switching frequency
increases with increasing reactive power, i.e. for excessive
reactive power levels, ZVS might be lost if e.g. due to
efficiency reasons an upper limit for the maximum switching
frequency is defined. The converter at hand is designed to
handle reactive powers of approximately ±30 % of the nom-
inal power. Nevertheless, compared to the conventional hard-
switched PWM topology with a constant switching frequency
of 10 kHz, with the iTCM concept, the semiconductor losses
can be significantly reduced, while at the same time the
average switching frequency is increased by more than a factor
of five, resulting in both, a higher efficiency and a higher power
density [25].
III. SYSTEM DESIGN
In the following, the design of the individual components of
the converter is presented, whereby TABLE I summarizes the
specifications of the system as a basis for the design process.
Current [A]
-15
-7.5
0
7.5
15
Current [A]
-30
-15
0
15
30
Frequency [kHz]
Time [ms]
0 2 4 6 8 10 12 14 16 18 20
0
20
40
60
80
i
b
i
Lg
i
g
i
A
i
f
i
f,50 Hz
f
sw
f
min
-I
ZVS
I
ZVS
Fig. 3: Ideal current waveforms of the iTCM converter considering the
capacitive line-frequency currents through C
b
and C
f
which cause a slight
asymmetry of the current ripples in L
b
and L
g
. In order to maintain a constant
turn-off current (as can be seen in the current i
A
), the switching frequency
pattern becomes asymmetric within one mains half-period.
TABLE I: System Specifications.
Parameter Value Parameter Value
P 25 kW f
min
35 kHz
U
AC
3.8 kV rms I
ZVS
4.5 A
U
DC
7 kV f
g
50 Hz
A. General MV SiC-Based Converter Design Considerations
In the following analysis, the iTCM converter with its DC-
link voltage of 7 kV and its power rating of 25 kW is compared
to a 400 V system with the same power rating, in order to
point out an important fundamental difference between the
design of MV converters and LV converters regarding parasitic
inductances and capacitances.
For each power electronic converter, a switching impedance,
i.e. the ratio between the switched voltage and the switched
current can be defined [28]:
Z
sw
= U
DC
/I
L
. (7)
This switching impedance is a useful quantity to analyze the
impact of parasitics on the switching behavior of a bridge leg.
For the analysis of the impact of parasitic inductances, the
schematic and the idealized waveforms given in Fig. 4(a) are
considered. If the low-side MOSFET turns off the current I
L
in a fixed switching time t
s
, a certain voltage u
σ
is induced
across the parasitic commutation loop inductance L
σ
, which
represents the sum of the MOSFET package inductances, the
PCB inductances, and the parasitic inductance of the DC-
link capacitor. This induced voltage is superimposed on the
low-side switch voltage u
S
and causes a voltage overshoot,
as shown in Fig. 4(a). If the impedance of the parasitic
commutation loop inductance L
σ
is in the same order of
magnitude as the switching impedance Z
sw
, the magnitude
of the voltage overshoot across the switch is for its part
in the same order of magnitude as the switched voltage.
Consequently, to limit the voltage overshoot to a certain value,
e.g. k
u
= 10 % of the DC-link voltage, an upper limit for the
This is the author's version of an article that has been published in this journal. Changes were made to this version by the publisher prior to publication.
The final version of record is available at http://dx.doi.org/10.1109/JESTPE.2018.2886140
Copyright (c) 2019 IEEE. Personal use is permitted. For any other purposes, permission must be obtained from the IEEE by emailing pubs-permissions@ieee.org.
![Fig. 8: Calorimetrically measured soft-switching losses with an external turnoff gate resistor of 10 Ω, taken from [29].](/figures/fig-8-calorimetrically-measured-soft-switching-losses-with-13q10oox.webp)