Proceedings ArticleDOI
A 1.8 V 3.2 /spl mu/W comparator for use in a CMOS imager column-level single-slope ADC
M.F. Snoeij,Albert J. P. Theuwissen,Johan H. Huijsing +2 more
- pp 6162-6165
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TLDR
Using this comparator design, the power consumption of column-level single-slope ADC of a CMOS imager can be reduced significantly.Abstract:
In this paper, a 1.8 V 3.2 /spl mu/W comparator is presented. It features a hybrid offset compensation scheme and achieves over 60 dB gain with an input offset below 150 /spl mu/V. The comparator is designed in a 0.18 /spl mu/m CMOS process and is specifically designed to be used as the key component of a column-level single-slope ADC of a CMOS imager. This ADC architecture is attractive because of its low noise, but so far this has come at the price of a relatively high power consumption. Using this comparator design, the power consumption of column-level single-slope ADC can be reduced significantly.read more
Citations
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Dissertation
CMOS Sensors for Time-Resolved Active Imaging
TL;DR: This chapter is intended to provide a history of the city and its people, as well as some of the characters and situations that have occurred in the city over the years.
Proceedings ArticleDOI
Low-power high-bandwidth preamplifier with improved common mode feedback stability
S Tarun Varma,B. Bhuvan +1 more
TL;DR: A low-power high feedback factor common mode feedback technique using subthreshold MOSFETs is presented in this paper, which is an improved version of the conventional resistive degeneration of current mirrors.
Journal ArticleDOI
Niskomocowy komparator z zatrzaskiem przeznaczony do cyfrowego przetwornika obrazu CMOS
TL;DR: W artykule zaproponowano realizacje analogowegó niskomocowego komparatora z zatrzaskiem przeznaczonego do cyfrowego piksela CMOS.
Proceedings ArticleDOI
High Resolution Comparator Design for RF Imager
TL;DR: A high resolution regenerative latch based comparator for Multi Ramp Multi slope ADC of RF 3D imager and fully differential architecture of the comparator noise immunity is high.
Proceedings ArticleDOI
A CMOS-only R-2R ladder D/A converter for image sensor applications
TL;DR: In this paper, a monotonic CMOS-only R-2R ladder D/A converter was used in a single-slope A/D converter for image sensor applications, which employs complementary switches with dummy transistors in the ladder to reduce the glitch energy of the output.
References
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Journal ArticleDOI
A 500-MSample/s, 6-bit Nyquist-rate ADC for disk-drive read-channel applications
I. Mehr,Declan M. Dalton +1 more
TL;DR: A 500MSam- ple/s 6-Bit ADC and its embedded implementation inside a disk drive read channel, using a 0.35µm CMOS single-poly, triple-metal process, achieves better than 5 effective number of bits (ENOB) for input frequencies up to Nyquist frequency and sampling frequencies fsup to 400MHz.
Proceedings ArticleDOI
A 500 msample/s 6–bit Nyquist rate ADC for disk drive read channel applications
I. Mehr,Declan M. Dalton +1 more
TL;DR: A 500MSam- ple/s 6-Bit ADC and its embedded implementation inside a disk drive read channel, using a 0.35µm CMOS single-poly, triple-metal process, achieves better than 5 effective number of bits (ENOB) for input frequencies up to Nyquist frequency and sampling frequencies f s up to 400MHz.
Proceedings ArticleDOI
SXGA pinned photodiode CMOS image sensor in 0.35 /spl mu/m technology
Keith Findlater,Robert Henderson,Donald Baxter,Jonathan Ephriam David Hurwitz,Lindsay A. Grant,Yvon Cazaux,F. Roy,Didier Herault,Y. Marcellier +8 more
TL;DR: In this paper, a 30 frames/s SXGA 5.6 /spl mu/m pinned photodiode pixel column parallel CMOS image sensor achieves 340 /spl µ/V noise floor and 40 pA/cm/sup 2/ dark current.