Proceedings ArticleDOI
A 20Gb/s Burst-Mode CDR Circuit Using Injection-Locking Technique
Jri Lee,Mingchung Liu +1 more
- pp 46-586
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TLDR
The design and experimental verification of a 20Gb/s CDR circuit based on injection-locking technique is presented that achieves a BER of <10-9 for both continuous and burst modes and has tunability of over 800Mb/s while consuming 175mW.Abstract:
The design and experimental verification of a 20Gb/s CDR circuit based on injection-locking technique is presented. Fabricated in 90nm CMOS technology, this circuit achieves a BER of <10-9 for both continuous and burst modes. It has tunability of over 800Mb/s while consuming 175mW. The re-acquisition time of this CDR is 1b interval.read more
Citations
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Journal ArticleDOI
A Low Jitter Programmable Clock Multiplier Based on a Pulse Injection-Locked Oscillator With a Highly-Digital Tuning Loop
TL;DR: A pulse injection-locked oscillator (PILO) that provides low jitter clock multiplication of a clean input reference clock using a mostly-digital feedback circuit that provides continuous tuning of the oscillator such that its natural frequency is locked to the injected frequency.
Journal ArticleDOI
Architectures for multi-gigabit wire-linked clock and data recovery
Ming-ta Hsieh,Gerald E. Sobelman +1 more
TL;DR: An overview and comparative study of the most commonly used CDR architectures is presented, which includes the circuit structures, design challenges, major performance limitations and primary applications.
Proceedings ArticleDOI
A 1.296-to-5.184Gb/s Transceiver with 2.4mW/(Gb/s) Burst-mode CDR using Dual-Edge Injection-Locked Oscillator
Kenichi Maruko,Tatsuya Sugioka,Hiroaki Hayashi,Zhiwei Zhou,Yasunori Tsukuda,Yuki Yagishita,Hironobu Konishi,Toshiyuki Ogata,Hisashi Owa,Taichi Niki,Kenji Konda,Masahiro Sato,Hiroshi Shiroshita,Takeshi Ogura,Takayuki Aoki,Hiroki Kihara,Sachiya Tanaka +16 more
TL;DR: The proposed CDR architecture, dual-edge injection-locked oscillator CDR (DILO-CDR), realizes fast lock (≪20 bits), continuous-rate capability (1.296 to 5.184Gb/s), and 2× power efficiency of previous fast-lock continuous- rate CDRs.
Proceedings ArticleDOI
A 1-to-6Gb/s phase-interpolator-based burst-mode CDR in 65nm CMOS
TL;DR: A BMCDR that is based on phase interpolation (PI), eliminating the possibility of local frequency offset between the reference and recovered clock and 1 to 6Gb/s operation in 65nm CMOS with a locking time of less than 1UI is presented.
Journal ArticleDOI
A 12 Gb/s 0.9 mW/Gb/s Wide-Bandwidth Injection-Type CDR in 28 nm CMOS With Reference-Free Frequency Capture
Masuda Takashi,Ryota Shinoda,Jeremy Chatwin,Jacob Adams Wysocki,Koki Uchino,Yoshifumi Miyajima,Ueno Yosuke,Kenichi Maruko,Zhiwei Zhou,Hideyuki Suzuki,Norio Shoji +10 more
TL;DR: A comparison with published results shows a substantial improvement on the trend of wide CDR bandwidth coupled to degraded power efficiency.
References
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Proceedings ArticleDOI
A 10 Gb/s burst-mode CDR IC in 0.13 /spl mu/m CMOS
Masafumi Nogawa,Kazuyoshi Nishimura,Shunji Kimura,Takeshi Yoshida,Tomoaki Kawamura,Minoru Togashi,Kiyomi Kumozaki,Yusuke Ohtomo +7 more
TL;DR: In this paper, a 10 Gb/s burst mode CDR (clock and data recovery) IC, that is eight times faster than previous burstmode ICs, is fabricated in a 0.13 /spl mu/m CMOS process.
Journal ArticleDOI
High-speed circuit designs for transmitters in broadband data links
TL;DR: Various high-speed techniques including internal peaking, differentially stacked inductor, and dual-loop PLL for wireline communications are proposed, analyzed, and verified by means of three independent circuits.
A 10-Gb/s Burst-Mode CDR IC in 0.13-um CMOS
Masafumi Nogawa,Kazuyoshi Nishimura,Shunji Kimura,Tomoaki Yoshida,Tomoaki Kawamura,Minoru Togashi,Kiyomi Kumozaki,Yusuke Ohtomo +7 more
Proceedings ArticleDOI
Full-rate injection-locked 10.3Gb/s clock and data recovery circuit in a 45GHz-f/sub T/ SiGe process
TL;DR: A 10.3Gb/s full-rate fully integrated injection-locked CDR circuit with a BER lower than 1e-12 over a 160MHz lock range with a 33V supply is presented.
Proceedings ArticleDOI
A 3.25 Gb/s injection locked CMOS clock recovery cell
TL;DR: A clock signal embedded in a NRZ (Non Return to Zero) 2/sup 31/-1 pseudo-random data stream is used to injection lock a slave CMOS LC tank circuit and a clock signal responsive to this stimulus is generated and used to capture the data.