406 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 59, NO. 2, FEBRUARY 2011
A 60-GHz CMOS VCO Using Capacitance-Splitting
and Gate–Drain Impedance-Balancing Techniques
Lianming Li, Student Member, IEEE, Patrick Reynaert, Member, IEEE, and Michiel S. J. Steyaert, Fellow, IEEE
Abstract—The design and measurement of a 60-GHz 90-nm
CMOS voltage-controlled oscillator is presented. To reduce the
power consumption and to improve the phase-noise performance,
a capacitance-splitting and a gate–drain impedance-balancing
techniques, which are realized with an inductive divider, are
proposed. With these techniques, the size of the cross-coupled pair
is reduced. Analysis of the proposed techniques shows that the
transistor
generation efficiency is improved and the oscillator
noise factor is reduced. Moreover, the tank loaded quality factor
is increased by balancing impedance levels across the transistor
terminals. The 60-GHz oscillator was fabricated in a 90-nm
CMOS technology. Under 0.6-V supply, the oscillator achieved a
tuning range from 61.1 to 66.7 GHz, consuming only 3.16 mW. At
64 GHz, the phase noise is
95 dBc/Hz at 1-MHz offset.
Index Terms—
oscillator, millimeter-wave oscillators, phase
noise, quality factor, voltage-controlled oscillator (VCO).
I. INTRODUCTION
A
S A critical element of a frequency synthesizer, the oscil-
lator phase noise has in many aspects a large impact on
the system performance. Signal selectivity and the bit-error rate
worsen significantly when the oscillator phase noise increases.
Also, the oscillator power consumption is important when
used in wireless applications. Recently, the 60-GHz wireless
personal area network (WPAN) standard IEEE 802.15.3c
was proposed. This new standard is very suitable for future
indoor network applications [1]. This standard uses advanced
modulation schemes, like orthogonal frequency division mul-
tiplexing quadrature amplitude modulation (OFDM-QAM),
to achieve network speed in the range of gigabits per second.
Unfortunately, these modulation schemes bring forth stringent
phase-noise requirements for the oscillator [2].
Due to technology scaling,
and of advanced
CMOS devices are now around 200 GHz or even higher.
Therefore, many millimeter-wave circuits can be fabricated
using a nanoscale CMOS technology with the advantages of
low-cost and high integration levels [3]–[5]. Recently, a number
of fundamental-frequency CMOS oscillators working around
60 GHz have been reported [6]–[13]. However, as mentioned
in [13], millimeter-wave oscillator design has many challenges
Manuscript received August 16, 2010; revised November 04, 2010; accepted
November 09, 2010. Date of publication December 30, 2010; date of current
version February 16, 2011.
The authors are with the Department of Electrical Engineering, Micro-
electronics and Sensors (ESAT-MICAS), Katholieke Universiteit Leuven,
B-3001 Leuven, Belgium (e-mail: lianming.li@esat.kuleuven.be; patrick.rey-
naert@esat.kuleuven.be; michiel.steyaert@kuleuven.be).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TMTT.2010.2095425
caused by the high operating frequency and the large required
tuning range. These challenges are summarized as follows:
1) the varactor quality factor is very low at 60 GHz, it is thus
very difficult to meet the system phase noise requirements;
2) the linearity of the
tank suffers from the nonlinear
capacitance contributed mainly by the active device and the
varactor; and 3) the tuning range has to be very large to cover
the wide frequency band around 60 GHz [1]. A very large
voltage-controlled oscillator (VCO) gain
is therefore
required. To linearize the
tank and to reduce the ,a
switched capacitance technique can be used, but only if switch
loss can be tolerated. Or to reduce the AM noise effect on the
phase noise, a switch tuning technique can be used if the layout
routing can be solved [13]. Combined with the bad reactive lin-
earity of the
tank, the stringent requirement makes
it very difficult to improve the phase noise. How to achieve low
phase noise while consuming low power is therefore still very
challenging for millimeter-wave oscillators.
To address the oscillator challenges, this paper presents a ca-
pacitive splitting and a gate–drain impedance-balancing tech-
niques, which are realized using an inductive divider [15]. In this
way, the active device size can be reduced by half, and therefore,
the power consumption is also reduced. Analysis also shows
that, with the proposed techniques, the
generation efficiency
of the differential cross-coupled pair is improved, whereas the
oscillator noise factor, and thus, the phase noise, are reduced.
Moreover, the tank loaded quality factor is increased.
Section II first reviews millimeter-wave oscillator
phase-noise generation mechanisms. The criteria to build a
good oscillator are then defined and the performance limitations
of millimeter-wave oscillators are identified. In Section III, a
capacitance-splitting technique is used to enhance the
gener-
ation efficiency at millimeter-wave frequencies. Regarding the
transistor terminal resistance difference, Section IV introduces
a gate–drain impedance-balancing technique. Its effect on the
oscillator noise factor and the loaded quality factor is then ana-
lyzed. In Section V, a prototype oscillator is implemented using
an inductive divider, and the transistor biasing point selection
is discussed. In Section VI, the oscillator measurement results
are presented. Final conclusions are drawn in Section VII.
II. D
ESIGN ISSUES IN CMOS MILLIMETER-WAVE OSCILLATORS
A. Phase-Noise Generation Mechanisms
As shown in Fig. 1, a simple cross-coupled oscillator con-
sists of three parts, which are: 1) an
tank for frequency se-
lection; 2) an active differential cross-coupled pair to compen-
sate the tank losses; and 3) buffer amplifiers to provide output
driving and isolation purposes. The capacitive loading from the
0018-9480/$26.00 © 2010 IEEE
LI et al.:60-GHzCMOSVCO 407
Fig. 1. Simple cross-coupled oscillator.
buffer amplifiers, the cross-coupled pair, and interconnection
lines makes it very difficult to achieve a large tuning range [13].
Two important mechanisms contribute to the phase noise
in an oscillator [14], [16]–[19]. One source of phase noise
is coming directly from the negative
transistors and the
resistive losses of the tank. These phase-noise generation
mechanisms are described by the Leeson formula (1) [16]
(1)
with
being the noise factor, being the Boltzmann con-
stant,
being the temperature, being the signal amplitude,
being the center frequency, and being the tank loaded
quality factor. According to (1), to achieve a good phase noise,
the tank loaded quality factor needs to be maximized. The signal
amplitude across the tank also needs to be maximized, but this
is limited by the transistor reliability issues.
A second source of phase noise comes indirectly via the con-
trol lines, power supply, and biasing circuitry. The AM noise
will be converted into phase noise by modulating the effec-
tive capacitance and the level of the harmonics [17], [19], [20].
Moreover, this phase-noise generation depends not only on the
tank quality factor, but also on the harmonic level [13], [17],
[21]. Since the
tank quality factor is very low at millimeter-
wave frequencies, this naturally sets some requirements on the
achievable linearity of the active device, i.e., a larger
is required [22].
To summarize, the design of an
oscillator is generally
divided into two aspects: one is to maximize the
tank
frequency selectivity, i.e., to maximize the tank loaded quality
factor
; the other is to reduce the phase-noise contribution
of the active devices. The latter can usually be done through
improving the cross-coupled pair linearity and preventing the
tail current noise from entering the tank with a filter or a capac-
itor [14], [23]. Here, to suppress the noise upconversion and to
improve the linearity of the cross-coupled pair, the tail current
is removed, leading to Fig. 2. This structure is usually called a
voltage biased oscillator [13], [14], whose main disadvantage is
that the oscillator is very sensitive to the power supply (typically
called frequency pushing). As pointed out in [13], a low-noise
low-dropout voltage regulator can solve this problem.
Fig. 2. Simple cross-coupled oscillator without tail current.
B. Performance Limitations in Millimeter-Wave Oscillators
The investigation below will show that, in high-frequency os-
cillators, the effect of the active device on the passive
tank
and the phase noise is very important. Before doing such inves-
tigation, let us firstly define a criterion for a good oscillator. An
oscillator can be generally split into a power source and a fre-
quency-selection tank. In a good oscillator, a power source sup-
plies the power periodically and efficiently to a frequency-selec-
tion tank. As shown in Fig. 2, the power source is an amplifier
(i.e., a cross-coupled pair), and the frequency selection tank is
realized with an
-circuit, whose impedance is at the
target operating frequency. Periodicity is essential in the oscil-
lator design, and the efficiency shows how well the oscillator is
constructed.
Generally, the active device working speed is the same as that
of the output signal, but to overcome the active device speed
limit, special techniques can be used to achieve an oscillation
signal with a frequency higher than the active device working
speed. For example, in oscillators using a push–push technique
[4], [5] or a linear superposition technique [24], the active device
working speed is lower. However, in these techniques, special
attention has to be paid to the oscillator working efficiency since
the output power is low.
Besides maximizing the tank quality factor, the efficiency of
oscillators can be improved by careful design of the amplifier in
the oscillator. To be more specific, as the driving part of the
tank, the amplifier (in this case, the cross-coupled pair) should
compensate the losses of the
tank efficiently without intro-
ducing too much loading on the
tank. Besides the loading,
the active device also affects the phase noise through the oscil-
lator noise factor
[14], [17], [25], given in (2) as follows:
(2)
Due to the excess loop gain
, the noise factor and
noise multiplication are increased [25].
depends on the tran-
sistor biasing, and is typically 2–3-in-deep submicrometer tech-
nologies [26].
At high frequency, the cross-coupled differential pair perfor-
mance is not good. This can be clearly seen in Fig. 3, which
plots the differential negative transconductance
versus fre-
quency. Fig. 4(a) depicts a simplified
simulation setup. The
negative
of the cross-coupled pair, calculated as ,
408 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 59, NO. 2, FEBRUARY 2011
Fig. 3. Negative versus frequency (the original differential cross-coupled
pair and its model).
Fig. 4. Negative simulation setup. (a) Original differential cross-coupled
pair. (b) Model.
decreases more than 30% from 20 to 100 GHz in a 90-nm tech-
nology. A first-order transistor model, given in Fig. 4(b), al-
lows to derive the negative
as a function of frequency. The
result of this analysis is plotted in Fig. 3 for comparison. Al-
though Fig. 4(b) depicts a first-order model, the model and sim-
ulation show the same trend. The decrease of the negative
with frequency is thus due to the bandwidth limitation of
the cross-coupled pair and the transistor resistive loading effect.
This loading effect is caused by the transistor terminal resis-
tive impedance
and . Fig. 5 shows the real parts of
the equivalent parallel input and output impedances of a tran-
sistor. At 60 GHz, the output resistance
is about 500
and the parallel input gate resistance is about four times
larger, i.e., 2.4 k
. This is caused by the gate resistance loss and
the nonquasi-static effect. The output impedance decreases with
frequency due to
shunt feedback. Both and will
introduce more loading on the
tank when the frequency in-
creases.
Since the transistor
is decreasing with frequency, a larger
transistor size is needed for oscillation startup at millimeter-
wave frequency. Suppose that the transistor size is increased,
its terminal parallel impedances will be reduced proportionally.
Analysis shows that a larger power will be consumed and more
resistive loading will be introduced into the
tank, thereby re-
ducing the tank loaded quality factor; hence, reducing the phase
noise performance. These phenomena show that regarding the
tank impedance
, the sizing and biasing of the active de-
vices is very critical in millimeter-wave oscillator design.
Fig. 5. Transistors’ real parts of parallel input and output impedances.
Fig. 6. Modified differential cross-coupled pair.
The discussion above clearly indicates that both the oscillator
noise factor and the tank loaded quality factor are a function of
the active devices. After arranging (1) into (3), one can easily
see that in order to reduce the phase noise for a certain signal
swing, an efficient loss compensation scheme is required while
minimizing the
(3)
III. C
APACITANCE-SPLITTING TECHNIQUE
A capacitance-splitting technique is introduced to solve the
bandwidth limitation of the cross-coupled pair, resulting in a
modified cross-coupled pair (see Fig. 6). An inductor is inserted
between the drain of one transistor and the gate of the other tran-
sistor. With help of the inductor, the cross-coupled pair para-
sitic capacitances are split. It can be understood intuitively that
the differential cross-coupled pair becomes distributed from a
lumped
generation cell.
In this way, the performance of the modified cross-coupled
pair is improved a lot, which can be clearly seen in Fig. 7.
Compared to the original cross-coupled pair with the same size,
the negative
at 60 GHz has been improved by about 30%,
meaning the transistor generation efficiency is improved.
Since the
generation efficiency of the modified cross-cou-
pled pair is much higher than the original one, the size of the
cross-coupled pair can be smaller, resulting in a lower power
consumption. The operating frequency of the oscillator using
the modified cross-coupled pair can also be higher when com-
pared to the original cross-coupled pair.
LI et al.:60-GHzCMOSVCO 409
Fig. 7. Negative
versus frequency (the original and modified differential
cross-coupled pair).
Fig. 8. Cross-coupled pair with the impedance-balance technique.
IV. GATE
–DRAIN IMPEDANCE-BALANCING TECHNIQUE FOR
MILLIMETER-WAVE
OSCILLATORS
The resistive impedances at the transistor gate and drain ter-
minal will reduce the
tank loaded quality factor. To solve
this problem, a gate–drain impedance-balancing technique is
proposed. This is motivated by taking into account the differ-
ence between the transistor’s equivalent parallel input (gate)
and parallel output (drain) resistances. The proposed technique
is shown in Fig. 8. An impedance-transformation block with a
voltage gain
is introduced between the gate and drain. From
Fig. 8, the small-signal loop gain of the oscillator can be written
as
Loop gain (4)
First suppose
, i.e., the gate and drain of the cross-cou-
pled pair are directly connected, as shown in Fig. 2. Cross-cou-
pled transistors with a certain size are required for the oscillation
startup. Simulations find the transistor’s parallel input
, and
parallel output resistances to be about 1.2 k and 250 ,
respectively. Now suppose the tank parallel impedance
is
designed to be constant. If an extra gain stage with the voltage
gain
is inserted between the gate and drain, according to (4),
the transistor sizes can be scaled down. Therefore, the terminal
parallel resistances of the transistors are scaled up proportion-
ally.
becomes 1.2 k and becomes 250 . With
the impedance-transformation block, the gate parallel resistance
is transformed into , i.e., k ,
and the transistor total parallel resistance
, the parallel resis-
tance of the transistor terminal impedance
and , can be
written as
(5)
Calculations find that, when
, transistor terminal
impedance
is largest, which is the optimum condition for
the tank loaded quality factor.
In this design, for layout convenience,
is set to 2. Since the
gate terminal parallel resistance
is about four times larger
than the drain parallel resistance
, the impedances between
the drain and gate side are now balanced
(6)
When compared to the case where
, it is found that,
when , the total transistor terminal resistance is about
32% higher. Therefore, the tank loaded quality factor
is
higher. In addition, according to (4), compared to the case where
, when , the power consumption can be decreased
by half.
Now let us look at the noise factor
. The noise factor of
the cross-coupled pair oscillator, for the proposed impedance-
balancing technique, can be derived as [26]
(7)
Interestingly, besides the reduction due to the smaller
, the
oscillator noise factor is reduced further when . There-
fore, at least 3-dB phase-noise reduction will be expected with
the proposed technique, which is verified by the test results. The
phase-noise reduction can be understood as follows: with the
impedance-transformation technique, the transistor size can be
reduced. It means that less noise from the transistor is injected
into the tank, thereby reducing the noise factor. In addition, the
passive amplification gain
in front of the transistor gate sup-
presses the transistor noise further, thus a lower noise factor is
achieved.
V. I
MPLEMENTATION OF A
PROTOTYPE LOW
PHASE-NOISE
OSCILLATOR
The prototype oscillator structure is shown in Fig. 9. In this
structure, to take advantage of both the capacitance-splitting
and the impedance-balancing technique, an inductive divider
is used. Inductors
and , whose values are equal to about
60 pH, are used to realize the impedance-transformation block
with the voltage gain
.
The proposed oscillator structure resembles a Hartley oscil-
lator [28]. However, the operation mechanism is different. This
can be understood when looking at the negative
genera-
tion mechanism and the feedback network connection. In the
Hartley oscillator, the negative
is generated with the tank
inherent phase inversion property. This generates the positive
feedback for the oscillation. In contrast, the positive feedback in
the proposed oscillator is realized with the cross-coupled pair,
resulting in the negative
. In the feedback network connection
of the Hartley oscillator, the MOS transistor source terminal is
410 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 59, NO. 2, FEBRUARY 2011
Fig. 9. Whole oscillator including the cascode buffer amplifier.
Fig. 10. LC tank model of prototype oscillator.
connected in between two inductors. If the coupling of the two
inductors is not perfect, there will be some leakage inductance
in series with the transistor source, and this leakage inductance
will affect the Hartley oscillator operation [29].
The
tank model of the prototype oscillator is given in
Fig. 10, with
being the varactor capacitance, being the
gate capacitance of the cross-coupled pair, being the para-
sitic capacitance including the cross-coupled pair drain capaci-
tance and interconnect line capacitance, and
being the buffer
amplifier input capacitance. For simplicity, the lossy element is
neglected. The proposed oscillator is a fourth-order system, and
it has two possible oscillation frequencies, shown in (8) at the
bottom of this page.
Simulations show that the circuit can only work at the lower
frequency because the loop gain at the higher frequency is too
low. From (8), we can see that due to the impedance transforma-
tion, the impact of the transistor gate capacitance on the oscilla-
tion frequency is two times as large as the effect of other capac-
itances. However, if there is no impedance transformation, the
transistor size would have to be doubled. This means that, when
compared to the case where
, the proposed technique has
no negative impact on the tuning range. Furthermore, according
Fig. 11. versus @ 60 GHz.
Fig. 12. versus @ 60 GHz.
to (8), since the capacitance is split by the inductor , the pro-
posed circuit can achieve a higher operating frequency. More-
over, the series
and help to suppress to a certain extent
the AM noise effect on the phase noise, which is caused by in-
ductive and capacitive power imbalance [21].
As mentioned before, the biasing of transistors is very crit-
ical for the millimeter-wave oscillator design. In the prototype
oscillator, the transistor biasing point is selected with respect
of the
generation efficiency, noise, speed, and linearity re-
quirement. With an
-parameter simulation at 60 GHz,
and versus the gate voltage are generated. As shown
in Fig. 11,
reduces when increases. This is a well-
known tradeoff between linearity and
generation efficiency.
is a bathtub curve, shown in Fig. 12. Based on this curve,
the voltage region around 0.6 V is a good biasing region. As
discussed in Section II, the degradation of
with frequency
requires biasing towards high . According to the
versus curve in Fig. 13, the region from 0.6 to 0.8 V looks
like an inverse bathtub, and it is very flat. Therefore, combining
the requirements on the noise, the
efficiency, linearity, and
(8)
