Journal ArticleDOI
A circuit level fault model for resistive bridges
TLDR
A physically realistic yet economical resistive bridge fault model to model delay faults as well as logic faults is proposed and an accurate yet simple delay calculation method is proposed.Abstract:
Delay faults are an increasingly important test challenge. Modeling bridge faults as delay faults helps delay tests to detect more bridge faults. Traditional bridge fault models are incomplete because these models only model the logic faults or these models are not efficient to use in delay tests for large circuits. In this article, we propose a physically realistic yet economical resistive bridge fault model to model delay faults as well as logic faults. An accurate yet simple delay calculation method is proposed. We also enumerate all possible fault behaviors and present the relationship between input patterns and output behaviors, which is useful in ATPG. Our fault simulation results show the benefit of at-speed tests.read more
Citations
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VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)
TL;DR: This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time- to-volume.
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VLSI Test Principles and Architectures: Design for Testability
TL;DR: A comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time to market and time-to-volume as mentioned in this paper.
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Electronic Design Automation: Synthesis, Verification, and Test
TL;DR: EDA/VLSI practitioners and researchers in need of fluency in an "adjacent" field will find this an invaluable reference to the basic EDA concepts, principles, data structures, algorithms, and architectures for the design, verification, and test of VLSI circuits.
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System-on-Chip Test Architectures: Nanometer Design for Testability
TL;DR: This book is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that will allow students, researchers, DFT practitioners, and V LSI designers to master quickly System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs.
Journal ArticleDOI
Stochastic formulation of SPICE-type electronic circuit simulation with polynomial chaos
Kai Strunz,Qianli Su +1 more
TL;DR: The case studies demonstrate that the novel methodology is computationally faster than the Monte Carlo method and more accurate and flexible than the root-sum-square method, which makes the stochastic circuit simulator, referred to as PolySPICE, a compelling candidate for the tolerance study of reliability-critical electronic circuits.
References
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Journal ArticleDOI
Asymptotic waveform evaluation for timing analysis
L.T. Pillage,R.A. Rohrer +1 more
TL;DR: Asymptotic waveform evaluation (AWE) provides a generalized approach to linear RLC circuit response approximations and reduces to the RC tree methods.
Book
Principles of CMOS VLSI Design: A Systems Perspective
Neil Weste,K Eshraghian +1 more
TL;DR: CMOS Circuit and Logic Design: The Complemenatry CMOS Inverter-DC Characteristics and Design Strategies.
PRINCIPLES OF CMOS VLSI DESIGN A Systems Perspective Second Edition
Neil Weste,Kamran Eshraghian +1 more
Abstract: Introduction to CMOS Circuits. Introduction. MOS Transistors. MOS Transistor Switches. CMOS Logic. Circuit Representations. CMOS Summary. MOS Transistor Theory. Introduction. MOS Device Design Equation. The Complemenatry CMOS Inverter-DC Characteristics. Alternate CMOS Inverters. The Differential Stage. The Transmission Gate. Bipolar Devices. CMOS Processing Technology. Silicon Semiconductor Technology: An Overview. CMOS Technologies. Layout Design Rules. CAD Issues. Circuit Characterization and Performance Estimation. Introduction. Resistance Estimation. Capacitance Estimation. Inductance. Switching Characteristics. CMOS Gate Transistor Sizing. Power Consumption. Determination of Conductor Size. Charge Sharing. Design Margining. Yield. Scaling of MOS Transistor Dimensions. CMOS Circuit and Logic Design. Introduction. CMOS Logic Structures. Basic Physical Design of Simple Logic Gates. Clocking Strategies. Physical and Electrical Design of Logic Gates. 10 Structures. Structured Design Strategies. Introduction. Design Economics. Design Strategies. Design Methods. CMOS Chip Design Options. Design Capture Tools. Design Verification Tools. CMOS Test Methodolgies. Introduction. Fault Models. Design for Testability. Automatic Test Pattern Generation. Design for Manufacturability. CMOS Subsystem Design. Introduction. Adders and Related Functions. Binary Counters. Multipliers and Filter Structures. Random Access and Serial Memory. Datapaths. FIR and IIR Filters. Finite State Machines. Programmable Logic Arrays. Random Control Logic.
Book ChapterDOI
Modeling the driving-point characteristic of resistive interconnect for accurate delay estimation
TL;DR: In this paper, a reduced-order approximation for the Taylor series expansion coefficients of the driving-point admittance of an RC tree is presented. But this algorithm is not suitable for the case of series resistance.
Journal ArticleDOI
Book Review: Principles of CMOS VLSI Design: A Systems Perspective
TL;DR: An Introduction to Microprocessors: THORN EMI HOME ELECTRONICS is a concise presentation of the functioning of a microprocessor and of the systems that can be constructed by interfacing.