Proceedings ArticleDOI
A dual redundancy radiation-hardened Flip-Flop based on C-element in 65nm process
Gibran Limi Jaya,Shoushun Chen,Siek Liter +2 more
- pp 1-4
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TLDR
A radiation-hardened flip-flop immune to the Single Event Upset (SEU) effect was achieved through the use of C-elements and redundant storage elements and was implemented using 48 transistors and occupied an area of 30.78 um2.Abstract:
We propose a radiation-hardened flip-flop immune to the Single Event Upset (SEU) effect. Immunity was achieved through the use of C-elements and redundant storage elements. We take advantage of the property of C-element in which it enters a high impedance mode when its inputs are of different logic values. Redundant storage nodes are then used to drive the C-elements so that a single upset pulse in any storage will be prevented from altering the state of the output of the Flip-Flop. The Flip-Flop was implemented using 48 transistors and occupied an area of 30.78 um2, using 65nm CMOS process. It consumed 22.6% less transistors as compared to the traditional SEU resilient TMR Flip-flop.read more
Citations
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Proceedings ArticleDOI
Dual-Interlocked-Storage-Cell-Based Double-Node-Upset Self-Recoverable Flip-Flop Design for Safety-Critical Applications
Aibin Yan,Zhelong Xu,Jie Cui,Zuobin Ying,Zhengfeng Huang,Huaguo Liang,Patrick Girard,Xiaoqing Wen +7 more
TL;DR: Compared with the state-of-the-art hardened flip-flop cells, the proposed DURI-FF cell achieves roughly 43% delay reduction at the cost of moderate silicon area and power dissipation.
Journal ArticleDOI
Categorization and SEU Fault Simulations of Radiation-Hardened-by-Design Flip-Flops
Ehab A. Hamed,Inhee Lee +1 more
TL;DR: Six well-known RHBD FFs architectures are simulated using a 180 nm CMOS process to show a fair comparison between them while the conventional Transmission Gate Flip-Flop is used as a reference design for this comparison.
Proceedings ArticleDOI
A Highly Reliable and Low Power RHBD Flip-Flop Cell for Aerospace Applications
TL;DR: In this article , a Highly reliable and Low power Radiation-hardened-by-design (RHBD) Flip-Flop cell, namely HLRFF, completely hardened against double-node upsets (DNUs), is proposed for aerospace applications.
Journal ArticleDOI
A Novel Radiation-Hardened CCDM-TSPC Compared with Seven Well-Known RHBD Flip-Flops in 180 nm CMOS Process
TL;DR: In this paper , a cross-connected dual modular redundant true single-phase clock (TSPC) D flip-flop was proposed to reduce the propagation time of the circuit.
Journal ArticleDOI
Design of Radiation Hardened Latch and Flip-Flop with Cost-Effectiveness for Low-Orbit Aerospace Applications
TL;DR: To meet the requirements of both costeffectiveness and high reliability for low-orbit aerospace applications, this paper first presents a radiation hardened latch design, namely HLCRT, and also presents a flip-flop, namelyHLCRT-FF that can tolerate SNUs and DNUs.
References
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Journal ArticleDOI
Design for soft error mitigation
TL;DR: Various SEU and SET mitigation schemes that could help the designer meet her or his goals are described.
Journal ArticleDOI
Current and Future Challenges in Radiation Effects on CMOS Electronics
TL;DR: In this paper, the authors examine the impact of recent developments and the challenges they present to the radiation effects community and discuss future radiation effects challenges as the electronics industry looks beyond Moore's law to alternatives to traditional CMOS technologies.
Proceedings ArticleDOI
Combinational Logic Soft Error Correction
TL;DR: Two techniques for correcting radiation-induced soft errors in combinational logic are presented - error correction using duplication, and error Correction using time-shifted outputs.
Proceedings ArticleDOI
Feedback Redundancy: A Power Efficient SEU-Tolerant Latch Design for Deep Sub-Micron Technologies
TL;DR: A novel SEU-tolerant latch where redundant feedback lines are used to mask the effects of SEUs and the results show that this latch consumes about 50% less power and occupies 42% less area than a TMR-latch.
Proceedings ArticleDOI
A TMR Scheme for SEU Mitigation in Scan Flip-Flops
TL;DR: A novel register design which can detect and correct soft errors, which can be operated as a simple scan flip-flop or scan hold flip- flop and thus is useful for system testability purposes.