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Journal ArticleDOI

A Fully Integrated Dual-Mode Highly Linear 2.4 GHz CMOS Power Amplifier for 4G WiMax Applications

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TLDR
A single-chip linear CMOS PA with sufficient power and linearity for emerging OFDM-based 4G WiMAX applications and a novel bypass network is introduced to ensure stability without sacrificing gain.
Abstract
In recent years, there has been tremendous interest in trying to implement the power amplifier in CMOS, due to its cost and integration benefits. Most of the high power (watt-level) CMOS PAs reported to date have not exhibited sufficient linearity required for next generation wireless standards. In this paper, we report a single-chip linear CMOS PA with sufficient power and linearity for emerging OFDM-based 4G WiMAX applications. This 90 nm 2.4 GHz CMOS linear power amplifier uses a two-stage transformer-based power combiner and produces a saturated output power of 30.1 dBm with 33% PAE and 28 dB small-signal gain. A novel bypass network is introduced to ensure stability without sacrificing gain. The choice of optimal biasing and capacitive compensation produces very flat AM-AM and AM-PM response up to high power. The PA has been tested with OFDM modulated signal and produces EVM better than -25 dB at 22.7 dBm average power. Graceful power back-off is demonstrated through turning off one of the stages, allowing low-power operation with enhanced efficiency.

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Citations
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Journal ArticleDOI

A 60-GHz Dual-Mode Class AB Power Amplifier in 40-nm CMOS

TL;DR: A 60-GHz dual-mode power amplifier is implemented in 40-nm bulk CMOS technology and a new transistor layout is proposed to minimize the device and interconnect parasitics while the neutralized amplifier stage is co-optimized with input transformer to improve the power gain and stability.
Journal ArticleDOI

An Efficient Mixed-Signal 2.4-GHz Polar Power Amplifier in 65-nm CMOS Technology

TL;DR: A 65-nm digitally modulated polar transmitter incorporates a fully integrated, efficient 2.4-GHz switching Inverse Class-D power amplifier and simple static predistortion helps the transmitter meet EVM and mask requirements of 802.11g 54-Mb/s WLAN data.
Journal ArticleDOI

Transformer-Based Uneven Doherty Power Amplifier in 90 nm CMOS for WLAN Applications

TL;DR: This paper presents a fully integrated transformer-based Doherty power amplifier in a standard 90 nm CMOS process using a novel asymmetrical series combining transformer to achieve uneven Doherty operation.
Journal ArticleDOI

Design of CMOS Power Amplifiers

TL;DR: The key technology and circuit design issues facing the design of an efficient linear RF CMOS power amplifier for modern communication standards incorporating high peak-to-average ratio signals are described and two fundamentally different approaches to tackle these problems are presented.
Journal ArticleDOI

A Linear Multi-Mode CMOS Power Amplifier With Discrete Resizing and Concurrent Power Combining Structure

TL;DR: A discrete resizing technique is introduced in combination with a parallel-combining transformer to improve efficiencies in lower-power modes of a multi-mode class-AB power amplifier (PA), which exhibits a peak output power of 31 dBm with a PAE of 34.8%.
References
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Journal ArticleDOI

Fully integrated CMOS power amplifier design using the distributed active-transformer architecture

TL;DR: In this article, a distributed active transformer is presented to combine several low-voltage push-pull amplifiers efficiently with their outputs in series to produce a larger output power while maintaining a 50/spl Omega/match.
Journal ArticleDOI

A 2.4-GHz 0.18-/spl mu/m CMOS self-biased cascode power amplifier

TL;DR: In this article, a two-stage self-biased cascode power amplifier in 0.18/spl mu/m CMOS process for Class-1 Bluetooth application is presented, which provides 23dBm output power with a power-added efficiency (PAE) of 42% at 2.4 GHz.
Journal ArticleDOI

Fully Integrated CMOS Power Amplifier With Efficiency Enhancement at Power Back-Off

TL;DR: This paper presents a new approach for power amplifier design using deep submicron CMOS technologies and a transformer based voltage combiner is proposed to combine power generated from several low-voltage CMOS amplifiers.
Journal ArticleDOI

A capacitance-compensation technique for improved linearity in CMOS class-AB power amplifiers

TL;DR: In this paper, a nonlinear capacitance-compensation technique is developed to help improve the linearity of CMOS class-AB power amplifiers, which involves placing a PMOS device alongside the NMOS device, such that the overall capacitance seen at the amplifier input is a constant, thus improving linearity.
Journal ArticleDOI

A 5.8 GHz 1 V Linear Power Amplifier Using a Novel On-Chip Transformer Power Combiner in Standard 90 nm CMOS

TL;DR: A fully integrated 5.8 GHz Class AB linear power amplifier in a standard 90 nm CMOS process using thin oxide transistors utilizes a novel on-chip transformer power combining network to achieve maximum output power and low insertion loss over the bandwidth of interest.
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