Open AccessJournal Article
A New Area and Power Efficient Single Edge Triggered Flip-Flop Structure for Low Data Activity and High Frequency Applications
Imran Khan,Mirza Tariq Beg +1 more
TLDR
The proposed flip-flop is the best energy efficient with the comparable power delay product (PDP) having an improvement of up to 61.53% in view of power consumption.Abstract:
In this work, a new area and power efficient single edge triggered flip-flop has been proposed. The proposed design is compared with six existing flip-flop designs. In the proposed design, the number of transistors is reduced to decrease the area. The number of clocked transistors of the devised flip-flop is also reduced to minimize the power consumption. As compared to the other state of the art single edge triggered flip-flop designs, the newly proposed design is the best energy efficient with the comparable power delay product (PDP) having an improvement of up to 61.53% in view of power consumption. The proposed flip-flop also has the lowest transistor count and the lowest area. The simulation results show that the proposed flip-flop is best suited for low power and low area systems especially for low data activity and high frequency applications. Keywords: PDP, reliability, delay, process node, clock frequencyread more
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References
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Journal ArticleDOI
Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems
TL;DR: A new simulation and optimization approach is presented, targeting both high-performance and power budget issues, and the analysis approach reveals the sources of performance and power-consumption bottlenecks in different design styles.
Journal ArticleDOI
High-performance energy-efficient D-flip-flop circuits
Uming Ko,Poras T. Balsara +1 more
TL;DR: Among the five DFF's compared, the proposed push-pull isolation circuit is found to be the fastest with the best energy efficiency.
Proceedings ArticleDOI
Analysis of soft error rate in flip-flops and scannable latches
TL;DR: In this article, the authors evaluate the critical charge for the susceptible nodes in each flip-flop and implement two hardening techniques to improve the overall robustness of the circuit, which leads to reduced power and area overhead.
Proceedings ArticleDOI
Dual-edge triggered static pulsed flip-flops
Aliakbar Ghadiri,Hamid Mahmoodi +1 more
TL;DR: Two simple structures of low-power dual-edge triggered static pulsed flip-flops (DSPFF) are presented that results in low power dissipation in clock distribution networks and power consumption is observed to be the lowest among all high-performance flip- flops and latches.
Proceedings ArticleDOI
An Area and Power Efficient Design of Single Edge Triggered D-Flip Flop
TL;DR: A single edge-triggered, static D flip-flop design suitable, for low power and low area requirements is proposed and it is indicated that the circuit is capable of significant power savings.
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