Proceedings ArticleDOI
A novel approach for constrained via minimization problem in VLSI channel routing
Bhaskar Das,Ashim Kumar Mahato,Ajoy Kumar Khan +2 more
- pp 145-149
TLDR
This paper presents a procedure to find out non essential vias in CVM problem and shows the experimental results and hardcopy solutions of some layout to prove that this approach obtains better results compared to conventional algorithms.Abstract:
Constrained Via Minimization is a typical problem in VLSI channel routing. The objective of via minimization is to improve the circuit performance and productivity and to reduce the completion rate of routing. In CVM problem, some vias may be non essential to the given layout. Here we have to be selected and remove from the layout. In this paper, we present a procedure to find out non essential vias. This procedure we used to solve constrained via minimization problems. Then, we show the experimental results and hardcopy solutions of some layout to prove that our approach obtains better results compared to conventional algorithms.read more
Citations
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Journal Article
An efficient approach to constrained via minimization for two-layer VLSI routing
TL;DR: In this article, a new approach is proposed for two-layer VLSI routing, which is able to handle any types of routing, and allows arbitrary number of wire segments split at a via candidate.
References
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Journal ArticleDOI
Layer assignment problem for three-layer routing
K.C. Chang,H.C. Du +1 more
TL;DR: It is shown that the CVM3 problem is NP-complete and a heuristic algorithm is proposed and the experimental results show that the proposed algorithm is efficient and generates fairly good solutions.
Proceedings ArticleDOI
Via Minimization by Layout Modification
D. F. Wong,Jingsheng Cong +1 more
TL;DR: The application of the proposed algorithm to various solutions to the Deutsch's difficult problem produces the fewest numbers of vias ever reported in the literature.
Proceedings ArticleDOI
Constrained via minimization with practical considerations for multi-layer VLSI/PCB routing problems
TL;DR: A Segment-Crossing Graph model is introduced, then ageuristic algorithm is introduced on the basis of this model and results show that 45 percent 05 vias minime% are obtained on an average.
Book
Some modified algorithms for Dijkstra's longest upsequence problem.
TL;DR: First Dijkstra's algorithm and then two new modified merge algorithms are derived and presented in detail, and parallels are drawn between algorithms for the longest upsequence problem and algorithms for sorting.
Journal ArticleDOI
A layout modification approach to via minimization
D.F. Wong,Jason Cong +1 more
TL;DR: The experimental results show that the algorithm is more effective in via reduction and more efficient in running time than conventional via minimization algorithms.