A novel third order Delta Sigma Modulator with one opamp shared among three integrator stages
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TLDR
A novel third order delta sigma modulator (DSM) is presented, which shares one opamp among three integrator stages through an optimal operation timing, which makes use of load capacitance differences betweenIntegrator stages.Abstract:
A novel third order delta sigma modulator (DSM) is presented. The third order loop filter in the proposed DSM shares one opamp among three integrator stages through an optimal operation timing, which makes use of load capacitance differences between integrator stages. The power dissipation of the proposed DSM is much lower than conventional third order DSM because power consuming blocks in the DSM are only one opamp and a comparator. The proposed DSM, designed on 0.35µm CMOS process under 3.3V supply achieves 1mW power dissipation with 100-11kHz band width and 96dB SQNR.read more
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Proceedings ArticleDOI
A 7.5mW 101dB SNR low-power high-performance audio delta-sigma modulator utilizing opamp sharing technique
TL;DR: A low power and high performance third order delta-sigma modulator for audio applications, fabricated in a 0.18/im CMOS process, that utilizes a third order noise shaping with only one opamp by using opamp sharing technique.
Journal ArticleDOI
A High Dynamic Range and Low Power Consumption Audio Delta-Sigma Modulator with Opamp Sharing Technique among Three Integrators
Journal ArticleDOI
High-Pass Sigma–Delta Modulator With Techniques of Operational Amplifier Sharing and Programmable Feedforward Coefficients for ECG Signal Acquisition
TL;DR: In this paper, a high-pass sigma-delta modulator (HPSDM) is proposed for ECG signal acquisition system using op-amp sharing and programmable feedforward coefficients.
Journal ArticleDOI
A third order delta-sigma modulator employing shared opamp technique for WCDMA on 0.18um CMOS
Ghazal A. Fahmy,Daisuke Kanemoto,Haruichi Kanaya,Keiji Yoshida,Ramesh K. Pokharel,Awinash Anand +5 more
TL;DR: A third orders delta-sigma modulator (DSM) has been designed utilizing shared opamp technique to reduce number of opamp required and decrease power consumption.
Proceedings ArticleDOI
Operational Amplifier Sharing Based High-Pass Sigma-Delta Modulator with Programmable Feedforward Coefficients for ECG Signal Acquisition
TL;DR: A high-pass sigma–delta modulator that uses operational amplifier (op-amp) sharing and programmable feed-forward coefficients is presented for an electrocardiography (ECG) signal detection system.
References
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Wideband low-distortion delta-sigma ADC topology
TL;DR: In this paper, a /spl Delta/spl Sigma/ topology with reduced sensitivity to opamp nonlinearities is described, which is effective even for very low oversampling ratios, and can be used for any modulation order.
Journal ArticleDOI
A 2.5 V 12 b 5 MSample/s pipelined CMOS ADC
P.C. Yu,Hae-Seung Lee +1 more
TL;DR: This 1.2 /spl mu/m, 33 mW analog-to-digital converter (ADC) demonstrates a family of power reduction techniques including a commutated feedback capacitor switching (CFCS), sharing of the second stage of an op amp between adjacent stages of a pipeline, reusing the first stage of a op amp as the comparator pre-amp, and exploiting parasitic capacitance as common-mode feedback capacitors.
Journal ArticleDOI
A multiplexed switched capacitor filter bank
TL;DR: In this paper, a technique is introduced which allows several integrator capacitors to be multiplexed onto a single operational amplifier, which can be shared by several switched capacitor filter channels, drastically reducing the number of op amps required for filter banks.
Journal ArticleDOI
Analysis of a Switched-Capacitor Second-Order Delta–Sigma Modulator Using Integrator Multiplexing
TL;DR: It is shown that in principle, integrator multiplexing can be generalized for higher order delta-sigma modulators.
Proceedings ArticleDOI
An oversampled sigma-delta A/D converter using time division multiplexed integrator
TL;DR: In this article, a small-scale sigma-delta modulator for a sigmoid A/D converter is presented, which employs a double-integration switched-capacitor architecture.