Journal ArticleDOI
A Simulation-Based Metric to Guide Glitch Power Reduction in Digital Circuits
Reads0
Chats0
TLDR
An algorithm to classify spurious transitions in the activity of a digital circuit as generated and propagated glitches during logic simulation and a criticality metric is computed to identify the nets where glitch minimization techniques are likely to provide the maximum benefit.Abstract:
In this paper, we propose an algorithm to classify spurious transitions in the activity of a digital circuit as generated and propagated glitches during logic simulation. Using the activities obtained, we compute a criticality metric to identify the nets where glitch minimization techniques are likely to provide the maximum benefit. The proposed metric provides insight into which techniques are best suited for use in glitch reduction for a given circuit. This enables targeted application of glitch reduction techniques. Experiments with several glitch intensive benchmarks show a faster convergence within fewer iterations to solutions with reduced glitch activity. We validate this observation by using the proposed metric to guide the application of some glitch reduction techniques and quantify the resultant savings. The proposed algorithm can be seamlessly incorporated in modern event-driven logic simulators.read more
Citations
More filters
Proceedings ArticleDOI
Methodology for Detecting Glitch on Clock, Reset and CDC path
TL;DR: In this paper, an attempt has been made to propose a methodology for detecting glitch on clock tree, reset trees, and clock domain crossing (CDC) paths, which will cause chip re-spins when detected late in the design cycle.
Proceedings ArticleDOI
Design of Low Power Adaptive Path Changing Glitch Free Radix-4, Radix-8 Multipliers
TL;DR: The proposed approach uses the RADix-4 and RADIX-8 models with a glitch optimization circuit to construct a low power adjustable path selective Booth Multiplier architecture that achieves low power elements after removal of glitch.
Proceedings ArticleDOI
Design of Low Power Adaptive Path Changing Glitch Free Radix-4, Radix-8 Multipliers
TL;DR: In this article , a low power adjustable path selective Booth multiplier architecture is proposed to reduce the number of multipliers in the multipliers by using low power techniques like clock gating and sequenced latching process.
Proceedings ArticleDOI
Functional Verification of Clock Domain Crossing in Register Transfer Level
TL;DR: In this article , a static timing analysis (STA) is used to verify cross-clock domain crossing (CDC) signals, which is a special and difficult verification difficulty for clock domain crossings.
Journal ArticleDOI
Geometric Programming Approach to Glitch Minimization via Gate Sizing
TL;DR: In this paper , an area-glitch minimization GP (AGM-GP) is proposed to reduce glitches while constraining area and adhering to a timing specification.
References
More filters
Journal ArticleDOI
A survey of power estimation techniques in VLSI circuits
TL;DR: A review of the power estimation techniques that have recently been proposed for very large scale integrated (VLSI) circuits is presented.
Proceedings ArticleDOI
Transition density, a stochastic measure of activity in digital circuits
TL;DR: A new measure of activity, called the transition density, is proposed, which may be defined as the “average switching rate” at a circuit node, based on a stochastic model of logic signals and an algorithm to propagate it from the primary inputs to internal and output nodes is presented.
Proceedings ArticleDOI
Switching Activity Analysis Considering Spatioternporal Correlations
TL;DR: This work presents techniques for computing the switching activities of all circuit nodes under pseudorandom or biased input sequences and assuming a zero delay mode of operation using a lag-one Markov Chain model.
Journal ArticleDOI
Power estimation techniques for FPGAs
Jason H. Anderson,Farid N. Najm +1 more
TL;DR: This paper considers early prediction of net activity and interconnect capacitance in field-programmable gate array (FPGA) designs and develops empirical prediction models for these parameters, suitable for use in power-aware layout synthesis, early power estimation/planning, and other applications.
Journal ArticleDOI
Glitch power minimization by selective gate freezing
TL;DR: An important feature of the proposed method is that it can be applied in place directly to layout-level descriptions; therefore, it guarantees very predictable results and minimizes the impact of the transformation on circuit size and speed.