Proceedings ArticleDOI
A Transition Isolation Scan Cell Design for Low Shift and Capture Power
Yi-Tsung Lin,Jiun-Lang Huang,Xiaoqing Wen +2 more
- pp 107-112
TLDR
Experimental results on larger ISCAS'89, ITC'99, and IWLS'05 benchmark circuits show that the proposed scan cell design lowers capture power consumptions with reasonable CPU times and test set inflation.Abstract:
Shift and capture power management has become indispensable for modern complex low-power designs. Excessive shift power increases test application time and may jeopardize the shift operation correctness, excessive capture power during at-speed scan testing may lead to yield loss. This paper proposes a scan cell design which isolates scan cells output transitions in both shift and capture modes. Experimental results on larger ISCAS'89, ITC'99, and IWLS'05 benchmark circuits show that the proposed scan cell design lowers capture power consumptions with reasonable CPU times and test set inflation.read more
Citations
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Proceedings ArticleDOI
A programmable method for low-power scan shift in SoC integrated circuits
Ran Wang,Bonita Bhaskaran,Karthikeyan Natarajan,Ayub Abdollahian,Kaushik Narayanun,Krishnendu Chakrabarty,Amit Sanghani +6 more
TL;DR: A programmable method for shift-clock stagger assignment to reduce power supply noise during system-on-chip (SoC) testing and a heuristic algorithm to derive optimal result for small-to-medium sized problems is presented.
Proceedings ArticleDOI
A scan shifting method based on clock gating of multiple groups for low power scan testing
TL;DR: A new scan shifting method based on clock gating of multiple groups by reducing toggle rate of the internal combinational logic is presented, which prevents cumulative transitions caused by shifting operations of the scan cells.
Proceedings ArticleDOI
Scan Chain Reordering-Aware X-Filling and Stitching for Scan Shift Power Reduction
TL;DR: This paper presents a new scan shift power reduction method based on a scan chain reordering (SR)-aware X-filling and a stitching method that improves scan shiftpower consumption on benchmark circuits in most cases.
Journal ArticleDOI
A novel scan architecture for low power scan-based testing
TL;DR: A novel area-efficient gating scan architecture that offers an integrated solution for reducing total average power in both scan cells and combinational part during shift mode and mitigate the number of transitions during shift and capture cycles is proposed.
Book
Testing of Interposer-Based 2.5D Integrated Circuits
Ran Wang,Krishnendu Chakrabarty +1 more
TL;DR: A test architecture using e-fuses for pre-bond interposer testing is proposed and a programmable method for shift-clock stagger assignment to reduce power supply noise during SoC die testing in 2.5D ICs is presented.
References
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Proceedings ArticleDOI
A case study of ir-drop in structured at-speed testing
TL;DR: This paper discusses the prac- tical issues associated with power consumption during at-speed tests, and delineates in more detail the nature of power-related phenomena encountered in structured speed tests.
Proceedings ArticleDOI
Minimized power consumption for scan-based BIST
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Proceedings ArticleDOI
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TL;DR: A method of adapting conventional scan architectures such that they operate in a low power mode during test so that they maintain the test times of the pre-adapted scan architectures.
Proceedings ArticleDOI
Preferred Fill: A Scalable Method to Reduce Capture Power for Scan Based Designs
TL;DR: Experimental results presented for benchmark and industrial circuits demonstrate the effectiveness of the proposed method called Preferred Fill to reduce average and peak power dissipation during capture cycles of launch off capture delay fault tests.
Journal ArticleDOI
Scan architecture with mutually exclusive scan segment activation for shift- and capture-power reduction
TL;DR: A scan architecture with mutually exclusive scan segment activation which overcomes the shortcomings of previous approaches and achieves both shift and capture-power reduction with no impact on the performance of the design, and with minimal impact on area and testing time.
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