Journal ArticleDOI
Analysis of the robustness of the TMR architecture in SRAM-based FPGAs
Luca Sterpone,Massimo Violante +1 more
TLDR
In this article, the authors present an analysis of the SEU effects in circuits hardened according to Triple Module Redundancy to investigate the possibilities of successfully applying TMR to designs mapped on commercial-off-the-shelf SRAM-based FPGAs, which are not radiation hardened.Abstract:
Non radiation-hardened SRAM-based Field Programmable Gate Arrays (FPGAs) are very sensitive to Single Event Upsets (SEUs) affecting their configuration memory and thus suitable hardening techniques are needed when they are intended to be deployed in critical applications. Triple Module Redundancy is a known solution for hardening digital logic against SEUs that is widely adopted for traditional techniques (like ASICs). In this paper we present an analysis of the SEU effects in circuits hardened according to the Triple Module Redundancy to investigate the possibilities of successfully applying TMR to designs mapped on commercial-off-the-shelf SRAM-based FPGAs, which are not radiation hardened. We performed different fault-injection experiments in the FPGA configuration memory implementing TMR designs and we observed that the percentage of SEUs escaping TMR could reach 13%. In this paper we report detailed evaluations of the effects of the observed failure rates, and we proposed a first step toward an improved TMR implementation.read more
Citations
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Journal ArticleDOI
An overview of reconfigurable hardware in embedded systems
TL;DR: An overview of reconfigurable computing in embedded systems, in terms of benefits it can provide, how it has already been used, design issues, and hurdles that have slowed its adoption are presented.
Journal ArticleDOI
Low energy single event upset/single event transient-tolerant latch for deep subMicron technologies
TL;DR: A novel SEU/SET-tolerant latch called feedback redundant SEU-tolerance latch (FERST) is presented, where redundant feedback lines are used to mask SEUs and delay elements are usedto filter SETs.
Journal ArticleDOI
A new analytical approach to estimate the effects of SEUs in TMR architectures implemented through SRAM-based FPGAs
Luca Sterpone,Massimo Violante +1 more
TL;DR: A new analytical approach is described to estimate the dependability of TMR designs implemented on SRAM-based FPGAs that is able to predict the effects of single event upsets with the same accuracy of fault injection but at a fraction of the fault-injection's execution time.
Proceedings ArticleDOI
Feedback Redundancy: A Power Efficient SEU-Tolerant Latch Design for Deep Sub-Micron Technologies
TL;DR: A novel SEU-tolerant latch where redundant feedback lines are used to mask the effects of SEUs and the results show that this latch consumes about 50% less power and occupies 42% less area than a TMR-latch.
Journal ArticleDOI
Selective Hardening for Neural Networks in FPGAs
TL;DR: This paper evaluates the effects of radiation-induced errors in the output correctness of two neural networks implemented in static random-access memory-based FPGAs and proposes a selective hardening strategy that triplicates only the most vulnerable layers of the neural network.
References
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Proceedings ArticleDOI
Designing fault tolerant systems into SRAM-based FPGAs
TL;DR: This paper discusses high level techniques for designing fault tolerant systems in SRAM-based FPGAs, without modification in the FPGA architecture, and presents some fault coverage results and a comparison with the TMR approach.
Proceedings ArticleDOI
A fault injection analysis of Virtex FPGA TMR design methodology
TL;DR: In this paper, the authors present the meaningful results of a single bit upset fault injection analysis performed in Virtex FPGA triple modular redundancy (TMR) design, each programmable bit upset able to cause an error in the TMR design has been investigated.
Journal ArticleDOI
Errata to “Identification and Classification of Single-Event Upsets in the Configuration Memory of SRAM-Based FPGAs”
M. Ceschia,Massimo Violante,M. Sonza-Reorda,Alessandro Paccagnella,Paolo Bernardi,Maurizio Rebaudengo,Damiano Bortolato,M. Bellato,P. Zambolin,A. Candelori +9 more
TL;DR: Radiation testing of a commercial-off-the-shelf SRAM-based field-programmable gate arrays (FPGAs) with heavy ions shows the FPGA look-up table (LUT) resources are the most sensitive to SEUs, whereas interconnect resources areThe most critical for the device cross section because they use the largest number of configuration bits.
Proceedings ArticleDOI
Evaluating the effects of SEUs affecting the configuration memory of an SRAM-based FPGA
M. Bellato,Paolo Bernardi,Damiano Bortolato,A. Candelori,M. Ceschia,Alessandro Paccagnella,Maurizio Rebaudengo,Matteo Sonza Reorda,Massimo Violante,P. Zambolin +9 more
TL;DR: This paper analyses the effects of single event upsets in an SRAM-based FPGA, with special emphasis for the transient faults affecting the configuration memory, and describes a method for obtaining the same result with similar devices.
Radiation testing update, seu mitigation, and availability analysis of the virtex fpga for space reconfigurable computing.
E. Fuller,M. Caffrey +1 more
TL;DR: Evaluation of total ionizing dose, heavy ion and proton characterization and upset detection and mitigation schemes have been performed on Virtex FPGAs fabricated on epitaxial silicon to evaluate the on-orbit radiation performance expected for this technology.