Journal ArticleDOI
Board Level Drop Impact—Fundamental and Parametric Analysis
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This article is published in Journal of Electronic Packaging.The article was published on 2005-12-01. It has received 45 citations till now. The article focuses on the topics: Drop impact.read more
Citations
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Journal ArticleDOI
A review of board level solder joints for mobile applications
TL;DR: This review focuses on the drop-impact reliability of lead-free solder joints that interconnect the integrated circuit (IC) component to the printed circuit board (PCB) and tin-rich lead- free solders exhibit significantly higher strain rate sensitivity than eutectic SnPb solder.
Journal ArticleDOI
Alloying modification of Sn–Ag–Cu solders by manganese and titanium
TL;DR: Effects of Mn and Ti additives on the microstructure and solidification behavior of Sn–1.0Ag–0.5Cu alloys (SAC105), as well as mechanical properties, were investigated and it is shown that the elastic modulus of SAC105 alloys decreased with only a minor alloying addition due to the shrunken eutectic regions and coarsened eutECTic microconstituents.
Journal ArticleDOI
A methodology for drop performance prediction and application for design optimization of chip scale packages
TL;DR: In this paper, a global-local approach is used to first determine the dynamic response of the board during drop and then to translate it into stresses and strain energy density in solder joints and intermetallic layers.
Journal ArticleDOI
Effects of different drop test conditions on board-level reliability of chip-scale packages
TL;DR: A fatigue reliability model that predicts the drop counts for different drop test conditions was established and numerical solutions of interfacial stresses, obtained by the transient finite element analysis, provided a supporting basis for the crack propagation observed from the experiments.
Journal ArticleDOI
New insights into board level drop impact
TL;DR: Using analytical relations that have been developed, it has been found that miniaturisation of interconnection with accompanying reduction in load bearing area is the most significant source of drop impact vulnerability.
References
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Proceedings ArticleDOI
BGA brittle fracture - alternative solder joint integrity test methods
TL;DR: In this article, the authors conducted a study on 27 unique package constructions, evaluated under a wide variety of test conditions, including high speed solder ball shear and pull testing.
Proceedings ArticleDOI
Drop impact survey of portable electronic products
TL;DR: In this paper, the authors examined the impact behavior of several mobile devices and personal digital assistants at various impact orientations using an orientation conlrollcd drop tester 111, where a high-speed camera was used to estimate the impact orientation.
Proceedings ArticleDOI
Drop impact test - mechanics & physics of failure
TL;DR: In this article, the physics of failure in board-level drop impact have been investigated and three finite element analyses have been performed to understand the failure in drop impact: (i) velocity impact of a PCB -model as a beam; (ii) velocity impacts of a drop assembly with centrally mounted package and (iii) impacts of solid elements with submodeling.
Proceedings ArticleDOI
Impact reliability of solder joints
TL;DR: In this paper, the impact toughness of solder joints was evaluated by means of a miniature Charpy test, in which the shear rate was approximately 1 m/s, and the results revealed the ductile-to-brittle transitions in the joints.
Proceedings ArticleDOI
Mechanical response of PCBs in portable electronic products during drop impact
TL;DR: In this article, the authors investigated the mechanical response of printed circuit boards (PCBs) inside portable consumer electronic products, when such products are subjected to drop impact and measured the board response via accelerations and strains at specified locations on the board.
Related Papers (5)
Advanced experimental and simulation techniques for analysis of dynamic responses during drop impact
Experimental studies of board-level reliability of chip-scale packages subjected to JEDEC drop test condition
Support excitation scheme for transient analysis of JEDEC board-level drop test
Chang-Lin Yeh,Yi-Shao Lai +1 more