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Book ChapterDOI

Cache attacks and countermeasures: the case of AES

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TLDR
In this article, the authors describe side-channel attacks based on inter-process leakage through the state of the CPU's memory cache, which can be used for cryptanalysis of cryptographic primitives that employ data-dependent table lookups.
Abstract
We describe several software side-channel attacks based on inter-process leakage through the state of the CPU’s memory cache. This leakage reveals memory access patterns, which can be used for cryptanalysis of cryptographic primitives that employ data-dependent table lookups. The attacks allow an unprivileged process to attack other processes running in parallel on the same processor, despite partitioning methods such as memory protection, sandboxing and virtualization. Some of our methods require only the ability to trigger services that perform encryption or MAC using the unknown key, such as encrypted disk partitions or secure network links. Moreover, we demonstrate an extremely strong type of attack, which requires knowledge of neither the specific plaintexts nor ciphertexts, and works by merely monitoring the effect of the cryptographic process on the cache. We discuss in detail several such attacks on AES, and experimentally demonstrate their applicability to real systems, such as OpenSSL and Linux’s dm-crypt encrypted partitions (in the latter case, the full key can be recovered after just 800 writes to the partition, taking 65 milliseconds). Finally, we describe several countermeasures for mitigating such attacks.

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Citations
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Proceedings ArticleDOI

(Mis)managed: A Novel TLB-based Covert Channel on GPUs

TL;DR: In this article, the authors show that two such features-unified virtual memory (UVM) and multi-process service (MPS)-primarily introduced to improve the programmability and efficiency of GPU kernels have an unexpected consequence-that of creating a novel covert-timing channel via the GPU's translation lookaside buffer (TLB) hierarchy.
Proceedings ArticleDOI

A security vulnerability analysis of SoCFPGA architectures

TL;DR: This article presents an attacker model and highlights three different types of attacks namely direct memory attacks, cache timing attacks, and rowhammer attacks that can be used on inadequately protected systems based on SoCFPGAs.
Journal ArticleDOI

Adaptive caches as a defense mechanism against cache side-channel attacks

TL;DR: This work explores the viability of using adaptive caches, which are conventionally used as a performance-oriented architectural feature, as a defense mechanism against cache side-channel attacks.

High-speed Cryptography and Cryptanalysis

TL;DR: This thesis considers two cryptanalytical applications with very di??erent performance bottlenecks and optimization requirements and describes software implementations of these primitives that set new speed records.
Journal ArticleDOI

Spy Cartel: Parallelizing Evict+Time-Based Cache Attacks on Last-Level Caches

TL;DR: It is shown how parallelization can be used to reduce the runtime and improve the attack’s success making it at par with L1 cache attacks, and a new methodology for LLC cache attacks is proposed, by which an attacker can maximize the attack success for a given time frame.
References
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Journal ArticleDOI

Software protection and simulation on oblivious RAMs

TL;DR: This paper shows how to do an on-line simulation of an arbitrary RAM by a probabilistic oblivious RAM with a polylogaithmic slowdown in the running time, and shows that a logarithmic slowdown is a lower bound.

Serpent: A Proposal for the Advanced Encryption Standard

TL;DR: A new block cipher is proposed that uses S-boxes similar to those of DES in a new structure that simultaneously allows a more rapid avalanche, a more efficient bitslice implementation, and an easy analysis that enables it to be more secure than three-key triple-DES.
Book ChapterDOI

A Fast New DES Implementation in Software

TL;DR: A new optimized standard implementation of DES on 64-bit processors is described, which is about twice faster than the fastest known standard DES implementation on the same processor.
Book ChapterDOI

A side-channel analysis resistant description of the AES s-box

TL;DR: This article introduces a new masking countermeasure which is not only secure against first-order side-channel attacks, but which also leads to relatively small implementations compared to other masking schemes implemented in dedicated hardware.
Book ChapterDOI

An ASIC Implementation of the AES SBoxes

TL;DR: This article presents a hardware implementation of the S-Boxes from the Advanced Encryption Standard (AES), and shows that a calculation of this function and its inverse can be done efficiently with combinational logic.
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