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Book ChapterDOI

Cache attacks and countermeasures: the case of AES

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TLDR
In this article, the authors describe side-channel attacks based on inter-process leakage through the state of the CPU's memory cache, which can be used for cryptanalysis of cryptographic primitives that employ data-dependent table lookups.
Abstract
We describe several software side-channel attacks based on inter-process leakage through the state of the CPU’s memory cache. This leakage reveals memory access patterns, which can be used for cryptanalysis of cryptographic primitives that employ data-dependent table lookups. The attacks allow an unprivileged process to attack other processes running in parallel on the same processor, despite partitioning methods such as memory protection, sandboxing and virtualization. Some of our methods require only the ability to trigger services that perform encryption or MAC using the unknown key, such as encrypted disk partitions or secure network links. Moreover, we demonstrate an extremely strong type of attack, which requires knowledge of neither the specific plaintexts nor ciphertexts, and works by merely monitoring the effect of the cryptographic process on the cache. We discuss in detail several such attacks on AES, and experimentally demonstrate their applicability to real systems, such as OpenSSL and Linux’s dm-crypt encrypted partitions (in the latter case, the full key can be recovered after just 800 writes to the partition, taking 65 milliseconds). Finally, we describe several countermeasures for mitigating such attacks.

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Proceedings Article

Prime+abort: a timer-free high-precision L3 cache attack using intel TSX

TL;DR: This work shows that PRIME+ABORT is not only invulnerable to important classes of defenses, it also outperforms state-of-the-art LLCPRIME+PROBE attacks in both accuracy and efficiency, having a maximum detection speed 3× higher than LLC PRIME+, on Intel's Skylake architecture while producing fewer false positives.
Proceedings ArticleDOI

Grand Pwning Unit: Accelerating Microarchitectural Attacks with the GPU

TL;DR: It is shown that an attacker can build all the necessary primitives for performing effective GPU-based microarchitectural attacks and that these primitives are all exposed to the web through standardized browser extensions, allowing side-channel and Rowhammer attacks from JavaScript.
Proceedings ArticleDOI

A Provably Secure and Efficient Countermeasure against Timing Attacks

TL;DR: This work shows that the amount of information about the key that an unknown-message attacker can extract from a deterministic side-channel is bounded from above by |O| log (n+1) bits, and derives a novel countermeasure against timing attacks.
Journal ArticleDOI

Speculative Taint Tracking (STT): A Comprehensive Protection for Speculatively Accessed Data

TL;DR: The main idea is that it is safe to execute and selectively forward the results of speculative instructions that read secrets, as long as it can prove that the forwarded results do not reach potential covert channels.
Book ChapterDOI

C5: Cross-Cores Cache Covert Channel

TL;DR: C5 is built, a covert channel that tackles addressing uncertainty without requiring any shared memory, making the covert channel fast and practical and one order of magnitude above previous cache-based covert channels in the same setup.
References
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Journal ArticleDOI

Software protection and simulation on oblivious RAMs

TL;DR: This paper shows how to do an on-line simulation of an arbitrary RAM by a probabilistic oblivious RAM with a polylogaithmic slowdown in the running time, and shows that a logarithmic slowdown is a lower bound.

Serpent: A Proposal for the Advanced Encryption Standard

TL;DR: A new block cipher is proposed that uses S-boxes similar to those of DES in a new structure that simultaneously allows a more rapid avalanche, a more efficient bitslice implementation, and an easy analysis that enables it to be more secure than three-key triple-DES.
Book ChapterDOI

A Fast New DES Implementation in Software

TL;DR: A new optimized standard implementation of DES on 64-bit processors is described, which is about twice faster than the fastest known standard DES implementation on the same processor.
Book ChapterDOI

A side-channel analysis resistant description of the AES s-box

TL;DR: This article introduces a new masking countermeasure which is not only secure against first-order side-channel attacks, but which also leads to relatively small implementations compared to other masking schemes implemented in dedicated hardware.
Book ChapterDOI

An ASIC Implementation of the AES SBoxes

TL;DR: This article presents a hardware implementation of the S-Boxes from the Advanced Encryption Standard (AES), and shows that a calculation of this function and its inverse can be done efficiently with combinational logic.
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