Patent
Capacitor that includes high permittivity capacitor dielectric
Yee-Chia Yeo,Chenming Hu +1 more
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TLDR
In this article, a decoupling capacitor is formed on a semiconductor substrate that includes a silicon surface layer, and a substantially flat bottom electrode is formed in a portion of the semiconductor surface layer.Abstract:
A decoupling capacitor is formed on a semiconductor substrate that includes a silicon surface layer. A substantially flat bottom electrode is formed in a portion of the semiconductor surface layer. A capacitor dielectric overlies the bottom electrode. The capacitor dielectric is formed from a high permittivity dielectric with a relative permittivity, preferably greater than about 5. The capacitor also includes a substantially flat top electrode that overlies the capacitor dielectric. In the preferred application, the top electrode is connected to a first reference voltage line and the bottom electrode is connected to a second reference voltage line.read more
Citations
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References
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Journal ArticleDOI
Defects in epitaxial multilayers: I. Misfit dislocations*
J.W. Matthews,A.E. Blakeslee +1 more
TL;DR: In this paper, it was shown that the interfaces between layers were made up of large coherent areas separated by long straight misfit dislocations and the Burgers vectors were inclined at 45° to (001) and were of type 1/2a.
Journal ArticleDOI
Defects associated with the accommodation of misfit between crystals
TL;DR: In this article, a substantial fraction of the defects in epitaxial thin films are formed to accommodate part of the misfit between the stress-free lattice parameters of film and substrate.
Journal ArticleDOI
Beyond the conventional transistor
TL;DR: In this paper, the authors focus on approaches to continue CMOS scaling by introducing new device structures and new materials, including high-dielectric-constant (high-k) gate dielectric, metal gate electrode, double-gate FET and strained-silicon FET.
Patent
Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture
Chenming Hu,Tsu-Jae King,Vivek Subramanian,Leland Chang,Xuejue Huang,Yang-Kyu Choi,Jakub Tadeusz Kedzierski,Nick Lindert,Jeffrey Bokor,Wen-Chin Lee +9 more
TL;DR: In this article, a planar MOSFET is fabricated in a silicon layer overlying an insulating layer (e.g., SIMOX) with the device extending from the insulating layers as a fin.