Journal ArticleDOI
Circuits for pseudoexhaustive test pattern generation
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TLDR
Implementation methods based on cyclic codes are presented for pseudoexhaustive testing of combinational logic networks with restricted output dependency, using a modified linear-feedback shift register to generate exhaustive test patterns for every output of the circuit.Abstract:
Implementation methods based on cyclic codes are presented for pseudoexhaustive testing of combinational logic networks with restricted output dependency. A modified linear-feedback shift register (LFSR) is used to generate exhaustive test patterns for every output of the circuit. All detectable, combinational faults (those that do not change a combinational circuit to a sequential circuit) in each cone of logic driving a single output are guaranteed to be detected. Examples indicate that LFSRs based on cyclic codes have lower hardware cost and shorter or comparable test lengths than other approaches. These test-pattern generators are well suited to applications where short testing time, low hardware overhead, and 100% single-stuck-at fault coverage are required. >read more
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References
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Journal ArticleDOI
Verification Testing—A Pseudoexhaustive Test Technique
TL;DR: A new approach to test pattern generation which is particularly suitable for self-test is described, which requires much less computation time and fault coverage is much higher—all irredundant multiple as well as single stuck faults are detected.
Journal ArticleDOI
Syndrome-Testable Design of Combinational Circuits
TL;DR: This paper focuses on classical testing of combinational circuits and the large storage requirement for a list of the fault-free response of the circuit to the test set.
Journal ArticleDOI
Random-pattern coverage enhancement and diagnosis for LSSD logic self-test
E. B. Eichelberger,E. Lindbloom +1 more
TL;DR: Embedded linear feedback shift registers can be used for logic component self-test and a procedure that supports net-level diagnosis for structured logic in the presence of random test-pattern generation and signature analysis is given.
Journal ArticleDOI
Pseudorandom Testing
TL;DR: Electrical circuits can be tested by applying pseudorandom patterns generated by a linear feedback shift register (LFSR) because no fault simulation is needed, and analysis of Pseudorandom testing requires the circuit detectability profile.
Journal ArticleDOI
Exhaustive Generation of Bit Patterns with Applications to VLSI Self-Testing
Barzilai,Coppersmith,Rosenberg +2 more
TL;DR: A simple and efficient solution to this problem, derived from the connections between polynomials over finite fields and linear feedback shift registers, is presented and applications to the problem of VLSI self-testing are discussed and illustrated.