Deposit-etch-deposit ozone/teos insulator layer method

TLDR: In this paper, a gap filling and self-planarizing silicon oxide insulator spacer layer within a patterned integrated circuit (PIIC) layer is proposed to fill the gap in the IC.

Abstract: A method for forming a gap-filling and self-planarizing silicon oxide insulator spacer layer within a patterned integrated circuit layer. Formed upon a semiconductor substrate is a patterned integrated circuit layer which is structured with a titanium nitride upper-most layer. The patterned integrated circuit layer also has at least one lower-lying layer formed of a material having a growth rate with respect to ozone assisted Chemical Vapor Deposited (CVD) silicon oxide layers greater than the growth rate of ozone assisted Chemical Vapor Deposited (CVD) silicon oxide layers upon titanium nitride. Formed within and upon the patterned integrated circuit layer is a silicon oxide insulator spacer layer deposited through an ozone assisted Chemical Vapor Deposition (CVD) process. The silicon oxide insulator spacer layer is formed until the surface of the titanium nitride upper-most layer is passivated with the silicon oxide insulator spacer layer. The silicon oxide insulator spacer layer is then etched from the surface of the titanium nitride upper-most layer. Finally, additional portions of the silicon oxide insulator spacer layer are sequentially deposited and etched until the surface of the silicon oxide insulator spacer layer over the lower layer(s) of the patterned integrated circuit layer is planar with the upper surface of the titanium nitride upper-most layer of the patterned integrated circuit layer.