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Book ChapterDOI

Design of a CMOS Bandgap Reference Voltage Using the OP AMP in 180 nm Process

TLDR
In this paper, a first-order CMOS Bandgap reference using an operational amplifier with negative feedback to improve the power supply rejection ratio (PSRR) and reduce the temperature coefficient (TC).
Abstract
This article proposes the implementation and design of a first-order CMOS Bandgap reference using an operational amplifier with negative feedback to improve the power supply rejection ratio (PSRR) and reduce the temperature coefficient (TC). The circuit is designed in 180 nm CMOS process technology and provides a reference output voltage of 1.2 V over an extended temperature range from −40 °C to 120 °C with a measured temperature coefficient of 54 ppm/°C. The BGR chip uses a 1.8 V supply.

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References
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Book

Design of Analog CMOS Integrated Circuits

Behzad Razavi
TL;DR: The analysis and design techniques of CMOS integrated circuits that practicing engineers need to master to succeed can be found in this article, where the authors describe the thought process behind each circuit topology, but also consider the rationale behind each modification.
Book

Voltage References: From Diodes to Precision High-Order Bandgap Circuits

TL;DR: This paper focuses on the design of Precision Reference Circuits for Bandgap Trimming Procedure for a Mixed-Mode (Both Voltage-Mode and Current-Mode) Output Stage, and the effect of the Resistors' Temperature Coefficient on a Reference with a Current- Mode Output Stage.
Journal Article

A Novel Low Temperature Coefficient Band-gap Reference without Resistors

TL;DR: The simulation results with Spice indicate that the proposed BGR circuit has a higher power supply rejection ratio (PSRR) and low temperature coefficient (TC) than the current mirror errors dependent on the supply voltage and temperature.
Proceedings ArticleDOI

Design of an improved bandgap reference in 180nm CMOS process technology

TL;DR: In this paper, a Bandgap reference circuit with 0.2ppm/low temperature coefficient in 180nm CMOS process technology has been implemented using Cadence Virtuoso and simulated using Spectre ADE. The circuit achieves a simulated output voltage reference of 1.12V at room temperature (27°C) with the temperature range of −40°C to +125°C under supply voltage of 0.8V.
Proceedings ArticleDOI

A 1.2 V, 33 ppm/°C, 40 nW, regeneration based BGR circuit for nanowatt CMOS LSIs

TL;DR: A regeneration based BGR circuit using positive feedback results in the positive temperature coeffecient of 2.34 mV/° C from the single stage at room temperature, which results in 60 % saving in power and over 80% saving in area, when compared with the state-of-the-art trimming less BGR circuits.
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