Proceedings ArticleDOI
Design of high performance power efficient flip flops using transmission gates
V. K. Aravind Lakshman,R. Sakthivel +1 more
- pp 1-4
TLDR
The comparison of performance for various circuits of flip flop, master-slave flip flops and transmission gates is shown and the proposed circuits are simulated and compared using 90nm and 45nm technology.Abstract:
Flip-flop plays a major role in designing a synchronous circuits and memory. In this paper we have shown the comparison of performance for various circuits of flip flops, master-slave flip flops and transmission gates. FFs are mostly used to collect the group of data for a storage purpose and the performance includes delay, area minimization and power reduction. The delay can be minimized by transistor sizing and variation of voltage. The proposed circuits are simulated and compared using 90nm and 45nm technology.read more
Citations
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Proceedings ArticleDOI
Low power XOR gate design and its applications
TL;DR: The methodology discussed in this paper, the same design for XOR logic can be made possible with 6 transistors, and this design consumes 50% less power than that of conventional Xor logic design with CMOS technology.
Performance Analysis of Reversible Sequential Circuits Based on Carbon NanoTube Field Effect Transistors (CNTFETs)
Maryam Shaveisi,Abbas Rezaei +1 more
TL;DR: In this paper, the authors presented the importance of reversible logic in designing of high performance and low power consumption digital circuits and investigated the various forms of sequential reversible circuits such as D, T, SR and JK flip-flops based on carbon nanotube field effect transistors.
Proceedings ArticleDOI
Analytical study of high performance flip-flop circuits based on performance measurements
Neha Raghav,Malti Bansal +1 more
TL;DR: The comparative study of various flip flops using The Clocked CMOS (C2MOS) register, True Single-Phase Clocked Register (TSPCR), Self-Gating Flipflop, Static Flip Flop is done.
Proceedings ArticleDOI
Analysis of Leakage Power Reduction Using LECTOR and ONOFIC Technique in Clock Gated Flip-Flop
TL;DR: Different ways of reducing leakage power in digital CMOS circuitry are described in this article , where ONOFIC and LECTOR techniques are used in D Flip-Flops (Transmission gate and C 2 MOS) to reduce leakage power.
Proceedings ArticleDOI
Analysis of Leakage Power Reduction Using LECTOR and ONOFIC Technique in Clock Gated Flip-Flop
Tinku Mistry,Sagar. G Yadav +1 more
TL;DR: Different ways of reducing leakage power in digital CMOS circuitry are described in this paper, which are carried out in LTSpice with 65nm PTM technology with a 0.9V power supply.
References
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Journal ArticleDOI
Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems
TL;DR: A new simulation and optimization approach is presented, targeting both high-performance and power budget issues, and the analysis approach reveals the sources of performance and power-consumption bottlenecks in different design styles.
Proceedings ArticleDOI
Flow-through latch and edge-triggered flip-flop hybrid elements
TL;DR: This paper describes a hybrid latch-flipflop (HLFF) timing methodology aimed at a substantial reduction in latch latency and clock load.
Journal ArticleDOI
New single-clock CMOS latches and flipflops with improved speed and power savings
Jiren Yuan,Christer Svensson +1 more
TL;DR: In the new differential flipflops, clock loads are minimized and logic-related transistors are purely n-type in both n- and p-latches, giving additional speed advantage to this kind of CMOS circuits.
Journal ArticleDOI
A 2.2 W, 80 MHz superscalar RISC microprocessor
Gianfranco Gerosa,S. Gary,C. Dietz,D. Pham,K. Hoover,Jose Alvarez,Hector Sanchez,P. Ippolito,Tai Ngo,S. Litch,J. Eno,J. Golab,N. Vanderschaaf,J. Kahle +13 more
TL;DR: Low-power design techniques are used throughout the entire design, including dynamically powered down execution units, resulting in workstation level performance packed into a low-power, low-cost design ideal for notebooks and desktop computers.
Journal ArticleDOI
High-performance and low-power conditional discharge flip-flop
TL;DR: In this paper, high-performance flip-flops are analyzed and classified into two categories: the conditional precharge and the conditional capture technologies, based on how to prevent or reduce the redundant internal switching activities.