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Proceedings ArticleDOI

Design of high performance power efficient flip flops using transmission gates

18 Mar 2016-pp 1-4
TL;DR: The comparison of performance for various circuits of flip flop, master-slave flip flops and transmission gates is shown and the proposed circuits are simulated and compared using 90nm and 45nm technology.
Abstract: Flip-flop plays a major role in designing a synchronous circuits and memory. In this paper we have shown the comparison of performance for various circuits of flip flops, master-slave flip flops and transmission gates. FFs are mostly used to collect the group of data for a storage purpose and the performance includes delay, area minimization and power reduction. The delay can be minimized by transistor sizing and variation of voltage. The proposed circuits are simulated and compared using 90nm and 45nm technology.
Citations
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Proceedings ArticleDOI
01 Feb 2017
TL;DR: The methodology discussed in this paper, the same design for XOR logic can be made possible with 6 transistors, and this design consumes 50% less power than that of conventional Xor logic design with CMOS technology.
Abstract: With advent of technology scaling, the prime objective of design i.e. low power consumption can be easily acquired. For any digital logic design the power consumption depends on; Supply voltage, number of transistors incorporated in circuit and scaling ratios of the same. As CMOS technology supports inversion logic designs; NAND & NOR structures are useful for converting any logic equation into physical level design that comprises of PMOS and NMOS transistors. In similar way, logic can be implemented in other styles as well, with the difference in number of transistors required. The conventional CMOS design for XOR logic can be possible with 8 or more than 8 transistors, with the methodology discussed in this paper, the same design for XOR logic can be made possible with 6 transistors. The proposed methodology consists of Pass transistor logic and Single feedback topology. This design consumes 50% less power than that of conventional XOR logic design with CMOS technology. Since the design for XOR logic, is useful for variety of applications such as Data encryption, Arithmetic circuits, Binary to Gray encoding etc. the XOR logic has been selected for design. The design explained in this paper is simulated with Cadence 90nm technology.

13 citations

DOI
20 Jun 2018
TL;DR: In this paper, the authors presented the importance of reversible logic in designing of high performance and low power consumption digital circuits and investigated the various forms of sequential reversible circuits such as D, T, SR and JK flip-flops based on carbon nanotube field effect transistors.
Abstract: Background and Objectives: This study presents the importance of reversible logic in designing of high performance and low power consumption digital circuits. In our research, the various forms of sequential reversible circuits such as D, T, SR and JK flip-flops are investigated based on carbon nanotube field-effect transistors. Methods: By simultaneous using of the reversible logic gates and carbon nanotube transistors in implementation of various flip-flops and introducing suitable transistor circuits of conventional reversible gates, all reversible flip-flops are simulated in two voltages, 0.3 and 0.5 Volt. The Hspice_H-2013.03-SP2 software is used to simulate these circuits using the 32nm CNTFET technology (the standard Stanford spice model). Results: The simulation results indicate a significant reduction in the average power consumption of D, T, SR and JK flip-flops, respectively about 99.98%, 82.79%, 60.46%, and 81.53%. Conclusion: Our results show that the proposed structures have achieved a high performance in terms of average power consumption and PDP.======================================================================================================Copyrights©2018 The author(s). This is an open access article distributed under the terms of the Creative Commons Attribution (CC BY 4.0), which permits unrestricted use, distribution, and reproduction in any medium, as long as the original authors and source are cited. No permission is required from the authors or the publishers.======================================================================================================

5 citations


Cites background from "Design of high performance power ef..."

  • ...8 45 nm CMOS D-FF [29] Hybrid Latch Flip Flop Classic 1....

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  • ...Peres Gate Fredkin Gate Feynman Gate Parameter CNTFET CNTFET CNTFET Technology 0.5 0.5 0.5 Supply Voltage (V) 12 4 6 Number of Transistors 7.827e-07 1.490e-08 7.964e-08 Average Power Consumption (W) 3.176e-05 1.416e-06 1.918e-05 Maximum Power Consumption (W) 2.525e-09 5.045e-09 2.531e-09 (Sec)Delay 1.976e-15 9.787e-17 2.016e-16 PDP (J) 4.289e-24 4.937e-27 5.102e-25 Energy Delay Product (EDP) (J×Sec) JK-FF SR-FF T-FF D FF2 D FF1 Peres gate Fredkin gate Feynman gate Parameter 0.3 0.5 0.3 0.3 0.5 0.5 0.5 0.5 Vdd (V) 3 1 3 3 1 3 3 3 N 32 32 32 32 32 32 32 32 Lg (nm) 32 32 32 32 32 32 32 32 Lss (nm) 32 32 32 32 32 32 32 32 Ldd (nm) 4 4 4 4 4 4 4 4 Tox (nm) 4 3 16 4 4 16 4 16 Kox 20 - 20 20 - 20 20 20 Pitch (nm) (73,0) (73,0) (53,0) (173,0) (173,0) (43,0) (43,0) (34,0) Chiral vector Design Type PDP(j) Average Power Consumption (W) Number of Transistors Supply Voltage(V) Technology Parameter Classic 1.130e-15 42.23e-06 18 1.8 180 nm CMOS D-FF [28] Pass Transistor Logic Flip Flop Classic 2.83e-15 5.469e-06 20 1.8 45 nm CMOS D-FF [29] Hybrid Latch Flip Flop Classic 1.58e-12 15.95e-06 17 1 90 nm CMOS D-FF [30] Classic 4.342e-17 2.60e-06 16 1.8 180 nm CMOS D-FF [31] Reversible 3.754e-16 1.445e-07 16 0.5 CNTFET D FF1 Reversible 3.711e-19 1.305e-10 4 0.3 CNTFET D FF2 Classic 0.878e-15 17.5e-06 22 0.9 Si-MOSFET T-FF [32] Design 1 Classic 0.501e-15 38.00e-06 16 0.9 CNTFET T-FF [32] Design 2 Reversible - 2.9826e-004 24 1 0.35 um CMOS T-FF [27] Reversible 1.659e-14 6.538e-06 18 0.3 CNTFET Proposed T-FF Classic - 16.976e-06 28 1 90 nm CMOS SR-FF [33] Classic - 7.512e-06 12 1.2 45 nm CMOS SR-FF [34] Clocked CMOS Flip-Flop Reversible 1.498e-14 2.970e-06 24 0.5 CNTFET Proposed SR-FF Classic 5.02e-12 2.510e-05 32 0.9 45 nm CMOS JK-FF [27] Standard CMOS Classic 5.37e-12 1.343e-05 40 0.9 45 nm CMOS JK-FF [27] Standard transmission-gate Classic 2.71e-14 1.119e-05 16 0.9 45 nm CMOS JK-FF [27] Modify gate Reversible 1.268e-14 4.635e-06 14 0.5 CNTFET Proposed JK-FF Table 14: Values of adjustable CNTFET parameters for all proposed reversible structures Table 15: Comparisons of various Flip-Flops circuits...

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Proceedings ArticleDOI
05 May 2017
TL;DR: The comparative study of various flip flops using The Clocked CMOS (C2MOS) register, True Single-Phase Clocked Register (TSPCR), Self-Gating Flipflop, Static Flip Flop is done.
Abstract: In designing synchronous circuits and memory elements, Flip-flops (FF) play an integral role. In the present era, the demand of area efficient, lesser delay, and faster devices are the major concern. This paper present the comparative study of Flip Flops in terms of area and delay. The problem of device size is very dominant today because the demand for small device size along with lesser number of transistors is increasing. And also for implementing a circuit, comparatively less number of transistors are preferred in comparison to conventionally used number of transistors, as it results in lesser number of switching activities. And smaller delay is preferred as it results in faster device along with faster response time of device. Hence, in this paper, the comparative study of various flip flops using The Clocked CMOS (C2MOS) register, True Single-Phase Clocked Register (TSPCR), Self-Gating Flip Flop, Static Flip Flop is done. The reduction in the delay is done by properly changing the size of transistor and alteration in the value of voltage. The circuits are simulated and correlated using 45nm technology.

2 citations


Cites background or methods from "Design of high performance power ef..."

  • ...In terms of the speed, delay and the response time of the circuit, the further improvement can bemade by changing and varying the voltage and by significantly increasing the size of the transistor [2]....

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  • ...In C2MOS register, when the master stage is ON or in conduction phase, the slave stage is OFF or in non- conducting phase....

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  • ...The delay of the C2MOS technique is comparably equal when comparingthe result with C2MOS designed in paper entitled design of high performance power efficient flip flops using transmission gates [2]....

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  • ...The working of the C2MOS Register module is basically done in two phases: 1....

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  • ...Fig 4: Schematic diagram of C(2)MOS [2]...

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Proceedings ArticleDOI
26 Aug 2022
TL;DR: Different ways of reducing leakage power in digital CMOS circuitry are described in this article , where ONOFIC and LECTOR techniques are used in D Flip-Flops (Transmission gate and C 2 MOS) to reduce leakage power.
Abstract: Clock gating is a common approach for minimizing dynamic power dissipation in synchronous circuits, and it can also assist in reducing the amount of power wasted by digital circuits. The system clock signal consumes the most power in an electronics product since it is responsible for component transition states, which often results in switching power consumption. Different ways of reducing leakage power in digital CMOS circuitry are described in this paper. ONOFIC and LECTOR techniques are used in D Flip-Flops (Transmission gate and C 2 MOS) to reduce leakage power. Digital circuits with optimized transistor sizing based on Logical Effort Theory (LE theory) have been implemented for high performance. The above-mentioned circuits are compared in terms of average power, delay, leakage power, and power- delay product (PDP). Circuit simulations are carried out in LTSpice with 65nm PTM technology with a 0.9V power supply.
Proceedings ArticleDOI
26 Aug 2022
TL;DR: Different ways of reducing leakage power in digital CMOS circuitry are described in this paper, which are carried out in LTSpice with 65nm PTM technology with a 0.9V power supply.
Abstract: Clock gating is a common approach for minimizing dynamic power dissipation in synchronous circuits, and it can also assist in reducing the amount of power wasted by digital circuits. The system clock signal consumes the most power in an electronics product since it is responsible for component transition states, which often results in switching power consumption. Different ways of reducing leakage power in digital CMOS circuitry are described in this paper. ONOFIC and LECTOR techniques are used in D Flip-Flops (Transmission gate and C2MOS) to reduce leakage power. Digital circuits with optimized transistor sizing based on Logical Effort Theory (LE theory) have been implemented for high performance. The above-mentioned circuits are compared in terms of average power, delay, leakage power, and power- delay product (PDP). Circuit simulations are carried out in LTSpice with 65nm PTM technology with a 0.9V power supply.
References
More filters
Journal ArticleDOI
TL;DR: A new simulation and optimization approach is presented, targeting both high-performance and power budget issues, and the analysis approach reveals the sources of performance and power-consumption bottlenecks in different design styles.
Abstract: In this paper, we propose a set of rules for consistent estimation of the real performance and power features of the flip-flop and master-slave latch structures. A new simulation and optimization approach is presented, targeting both high-performance and power budget issues. The analysis approach reveals the sources of performance and power-consumption bottlenecks in different design styles. Certain misleading parameters have been properly modified and weighted to reflect the real properties of the compared structures. Furthermore, the results of the comparison of representative master-slave latches and flip-flops illustrate the advantages of our approach and the suitability of different design styles for high-performance and low-power applications.

660 citations


"Design of high performance power ef..." refers background in this paper

  • ...2016 International Conference on Circuit, Power and Computing Technologies [ICCPCT] the power distribution [4]....

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  • ...MODIFIED C2MOS LATCH Modified C2MOS master slave latch is simple and symmetric in structure [4]....

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  • ...Power delay product is very less because of this the speed of the circuit can be increased [4]....

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  • ...The minimum time between a data change and the trigger edge of clock pulse is defined as setup time, by assuming the wide clock pulse the output will be guaranteed to change as to become equal to new data value [4]....

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  • ...The main advantage of this circuit is because of its robustness to clock skew [4]....

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Proceedings ArticleDOI
08 Feb 1996
TL;DR: This paper describes a hybrid latch-flipflop (HLFF) timing methodology aimed at a substantial reduction in latch latency and clock load.
Abstract: This paper describes a hybrid latch-flipflop (HLFF) timing methodology aimed at a substantial reduction in latch latency and clock load. A common principle is employed to derive consistent latching structures for static logic, dynamic domino and self-resetting logic.

385 citations

Journal ArticleDOI
TL;DR: In the new differential flipflops, clock loads are minimized and logic-related transistors are purely n-type in both n- and p-latches, giving additional speed advantage to this kind of CMOS circuits.
Abstract: New dynamic, semistatic, and fully static single-clock CMOS latches and flipflops are proposed. By removing the speed and power bottlenecks of the original true-single-phase clocking (TSPC) and the existing differential latches and flipflops, both delays and power consumptions are considerably reduced. For the nondifferential dynamic, the differential dynamic, the semistatic, and the fully static flipflops, the best reduction factors are 1.3, 2.1, 2.2, and 2.4 for delays and 1.9, 3.5, 3.4, and 6.5 for power-delay products with an average activity ratio (0.25), respectively. The total and the clocked transistor numbers are decreased. In the new differential flipflops, clock loads are minimized and logic-related transistors are purely n-type in both n- and p-latches, giving additional speed advantage to this kind of CMOS circuits.

270 citations


"Design of high performance power ef..." refers background in this paper

  • ...[2] Jiren Yuan and Christer Svensson,” New single clock CMOS latches and flipflops with improved speed and power saving” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL....

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Journal ArticleDOI
01 Dec 1994
TL;DR: Low-power design techniques are used throughout the entire design, including dynamically powered down execution units, resulting in workstation level performance packed into a low-power, low-cost design ideal for notebooks and desktop computers.
Abstract: A 28 mW/MHz at 80 MHz structured-custom RISC microprocessor design is described. This 32-b implementation of the PowerPC architecture is fabricated in a 3.3 V, 0.5 /spl mu/m, 4-level metal CMOS technology, resulting in 1.6 million transistors in a 7.4 mm by 11.5 mm chip size. Dual 8-kilobyte instruction and data caches coupled to a high performance 32/64-b system bus and separate execution units (float, integer, loadstore, and system units) result in peak instruction rates of three instructions per clock cycle. Low-power design techniques are used throughout the entire design, including dynamically powered down execution units. Typical power dissipation is kept under 2.2 W at 80 MHz. Three distinct levels of software-programmable, static, low-power operation-for system power management are offered, resulting in standby power dissipation from 2 mW to 350 mW. CPU to bus clock ratios of 1/spl times/, 2/spl times/, 3/spl times/, and 4/spl times/ are implemented to allow control of system power while maintaining processor performance. As a result, workstation level performance is packed into a low-power, low-cost design ideal for notebooks and desktop computers. >

229 citations

Journal ArticleDOI
TL;DR: In this paper, high-performance flip-flops are analyzed and classified into two categories: the conditional precharge and the conditional capture technologies, based on how to prevent or reduce the redundant internal switching activities.
Abstract: In this paper, high-performance flip-flops are analyzed and classified into two categories: the conditional precharge and the conditional capture technologies. This classification is based on how to prevent or reduce the redundant internal switching activities. A new flip-flop is introduced: the conditional discharge flip-flop (CDFF). It is based on a new technology, known as the conditional discharge technology. This CDFF not only reduces the internal switching activities, but also generates less glitches at the output, while maintaining the negative setup time and small D-to-Q delay characteristics. With a data-switching activity of 37.5%, the proposed flip-flop can save up to 39% of the energy with the same speed as that for the fastest pulsed flip-flops.

204 citations