Proceedings ArticleDOI
Flow-through latch and edge-triggered flip-flop hybrid elements
Hamid Partovi,R. Burd,U. Salim,Frederick Weber,L. DiGregorio,Donald A. Draper +5 more
- pp 138-139
TLDR
This paper describes a hybrid latch-flipflop (HLFF) timing methodology aimed at a substantial reduction in latch latency and clock load.Abstract:Â
This paper describes a hybrid latch-flipflop (HLFF) timing methodology aimed at a substantial reduction in latch latency and clock load. A common principle is employed to derive consistent latching structures for static logic, dynamic domino and self-resetting logic.read more
Citations
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Journal ArticleDOI
Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems
TL;DR: A new simulation and optimization approach is presented, targeting both high-performance and power budget issues, and the analysis approach reveals the sources of performance and power-consumption bottlenecks in different design styles.
Journal ArticleDOI
Improved sense-amplifier-based flip-flop: design and measurements
Borivoje Nikolic,Vojin G. Oklobdzija,Vladimir Stojanovic,Wenyan Jia,James Kar Shing Chiu,M. Ming-Tak Leung +5 more
TL;DR: The design and experimental evaluation of a new sense-amplifier-based flip-flop (SAFF) is presented and it is found that the main speed bottleneck of existing SAFF's is the cross-coupled set-reset (SR) latch in the output stage.
Journal ArticleDOI
High-performance and low-power conditional discharge flip-flop
TL;DR: In this paper, high-performance flip-flops are analyzed and classified into two categories: the conditional precharge and the conditional capture technologies, based on how to prevent or reduce the redundant internal switching activities.
Journal ArticleDOI
The implementation of the Itanium 2 microprocessor
S.D. Naffziger,Glenn T. Colon-Bonet,T. Fischer,Reid James Riedlinger,Thomas J Sullivan,T. Grutkowski +5 more
TL;DR: This 64-b microprocessor is the second-generation design of the new Itanium architecture, termed explicitly parallel instruction computing (EPIC), and seeks to extract maximum performance from EPIC by optimizing the memory system and execution resources for a combination of high bandwidth and low latency.
Journal ArticleDOI
Conditional-capture flip-flop for statistical power reduction
TL;DR: The simulation comparison indicates that the proposed differential flip-flop achieves power savings of up to 61% with no impact on latency while the single-ended structure provides the maximum power Savings of around 67%, as compared to conventional flip- flops.
References
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Journal ArticleDOI
A 200-MHz 64-b dual-issue CMOS microprocessor
Daniel W. Dobberpuhl,R. Witek,R. Allmon,R. Anglin,D. Bertucci,S.M. Britton,L. Chao,R.A. Conrad,D.E. Dever,B. Gieseke,Soha Hassoun,G. Hoeppner,K. Kuchler,M. Ladd,B.M. Leary,L. Madden,Edward J. McLellan,D.R. Meyer,J. Montanaro,Donald A. Priore,V. Rajagopalan,S. Samudrala,S. Santhanam +22 more
TL;DR: A RISC (reduced-instruction-set computer)-style microprocessor operating up to 200 MHz, implements a 64-b architecture that provides huge linear address space without bottlenecks that would impede highly concurrent implementations.
Journal ArticleDOI
A 2-ns cycle, 3.8-ns access 512-kb CMOS ECL SRAM with a fully pipelined architecture
Terry I. Chappell,B.A. Chappell,Stanley E. Schuster,J.W. Allan,S.P. Klepner,Rajiv V. Joshi,R.L. Franch +6 more
TL;DR: In this article, the authors describe a 512 K CMOS static RAM (SRAM) with emitter-coupled-logic (ECL) interfaces which has a 2-ns cycle time and a 3.8-ns access time, both of which are valid for random READ/WRITE operations.