Journal ArticleDOI
Dynamic power-aware scheduling of real-time tasks for FPGA-based cyber physical systems against power draining hardware trojan attacks
TLDR
This work explores how power draining ability of HTHs may reduce lifetime of the system and an offline–online scheduling strategy is proposed for periodic tasks which can ensure reliability of their operations till the expected lifetime ofThe system.Abstract:
The present era has witnessed deployment of reconfigurable hardware or field-programmable gate arrays (FPGAs) in diverse domains like automation and avionics, which are cyber physical in nature. Such cyber physical systems are associated with strict power budgets. Efficient real-time task-scheduling strategies exist that ensure execution of maximum number of tasks within the power budget. However, these do not consider hardware threats into account. Recent literature has exposed the existence of hardware trojan horses (HTHs). HTHs are malicious circuitry that remain dormant during testing and evade detection, but get activated at runtime to jeopardize operations. HTHs can be etched into the FPGA fabric by adversaries in the untrustworthy foundries, during fabrication of the FPGAs. Even vendors selling reconfigurable intellectual properties or bitstreams that configure the FPGA fabric for task operation may insert HTHs during writing the bitstream codes. HTHs may cause a variety of attacks which may affect the basic security primitives of the system like its integrity, confidentiality or availability. In this work, we explore how power draining ability of HTHs may reduce lifetime of the system. A self-aware approach is also proposed which detects the affected resources of the system and eradicates their use in future to facilitate system reliability. An offline–online scheduling strategy is proposed for periodic tasks which can ensure reliability of their operations till the expected lifetime of the system. Accommodating non-periodic tasks in the periodic task schedule based on available power is also focused. For experimentation, we consider tasks associated with EPFL benchmarks and demonstrate results based on the metric task success rate for periodic tasks and metric task rejection rate for non-periodic tasks.read more
Citations
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Proceedings Article
Modular dynamic reconfiguration in Virtex FPGAs
TL;DR: Two methods for implementing modular reconfiguration in Virtex FPGAs are compared and contrasted and the second method, developed recently, enables modules to be allocated arbitrary areas of the FPGA, bridging the gap between theory and reality and unlocking the latent potential of dynamic reconfigurations.
Journal ArticleDOI
Minimization of WCRT with Recovery Assurance from Hardware Trojans for Tasks on FPGA-based Cloud
Debasri Saha,Susmita Sur-Kolay +1 more
TL;DR: Dynamic partial reconfiguration (DPR) enabled FPGA-based Cloud architecture acts as a flexible and efficient shared environment to facilitates application support to users' request at low cost.
Book ChapterDOI
Introduction to Hardware Security for FPGA Based Systems
TL;DR: In this paper, the authors proposed a method to detect power dissipation attacks that may affect the green computing factor of a system or may drain the power budget of the system and cause early expiry of the computer system.
Proceedings ArticleDOI
SENAS: Security driven ENergy Aware Scheduler for Real Time Approximate Computing Tasks on Multi-Processor Systems
TL;DR: In this article , the authors proposed a security driven ENergy Aware Scheduler (SENAS) that works as a self-aware agent to decide which task is to be executed in which processor of a system.
References
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Journal ArticleDOI
Hardware Trojan Attacks: Threat Analysis and Countermeasures
TL;DR: The threat of hardware Trojan attacks is analyzed; attack models, types, and scenarios are presented; different forms of protection approaches are discussed; and emerging attack modes, defenses, and future research pathways are described.
Book ChapterDOI
MERO: A Statistical Approach for Hardware Trojan Detection
TL;DR: A test pattern generation technique based on multiple excitation of rare logic conditions at internal nodes that maximizes the probability of inserted Trojans getting triggered and detected by logic testing, while drastically reducing the number of vectors compared to a weighted random pattern based test generation.
Journal ArticleDOI
Hardware Trojan Detection by Multiple-Parameter Side-Channel Analysis
Seetharam Narasimhan,Dongdong Du,Rajat Subhra Chakraborty,Somnath Paul,Francis Wolff,Christos A. Papachristou,Kaushik Roy,Swarup Bhunia +7 more
TL;DR: A novel noninvasive, multiple-parameter side-channel analysisbased Trojan detection approach that uses the intrinsic relationship between dynamic current and maximum operating frequency of a circuit to isolate the effect of a Trojan circuit from process noise.
The EPFL Combinational Benchmark Suite
TL;DR: The EPFL combinational benchmark suite consists of 23 combinational circuits designed to challenge modern logic optimization tools, available to the public and distributed in all Verilog, VHDL, BLIF and AIGER formats.
Journal ArticleDOI
Modular dynamic reconfiguration in Virtex FPGAs
TL;DR: In this paper, the authors compare and contrast two methods for implementing modular reconfiguration in Virtex FPGAs, one of which offers simplicity and fast reconfigure times, but limits the geometry and connectivity of the system.
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