Journal ArticleDOI
Fabrication Methods for Nanowire Tunnel FET with Locally Concentrated Silicon-germanium Channel
Junil Lee,Ryoongbin Lee,Sihyun Kim,Euyhwan Park,Hyun-Min Kim,Kitae Lee,Sangwan Kim,Byung-Gook Park +7 more
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This article is published in Journal of Semiconductor Technology and Science.The article was published on 2019-02-28. It has received 4 citations till now. The article focuses on the topics: Communication channel & Silicon-germanium.read more
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Journal ArticleDOI
Two-dimensional analytical modeling for electrical characteristics of Ge/Si SOI-tunnel FinFETs
Sweta Chander,Srimanta Baishya,Sanjeet Kumar Sinha,Sunil Kumar,Prince Kumar Singh,Kamalaksha Baral,Manas Ranjan Tripathy,Ashish Kumar Singh,Satyabrata Jit +8 more
TL;DR: In this article, a two-dimensional analytical model for surface potential, electric field, drain current and threshold voltage of a three-dimensional (3D) Ge/Si heterojunction SOI-Tunnel FinFET (TFinFET) with a SiO2/HfO2 stacked gate oxide structure is presented.
Journal ArticleDOI
Switching Performance Investigation of a Gate-All-Around Core-Source InGaAs/InP TFET
TL;DR: In this article, a core-source gate-all-around TFET based on InGaAs/InP heterojunction is presented, where the main current flow mechanism is line tunneling which occurs across a heterjunction composed of a narrowbandgap material of source and a wide-band gap material of channel.
Journal ArticleDOI
Si‐core/SiGe‐shell channel nanowire FET for sub‐10‐nm logic technology in the THz regime
Eunseon Yu,Baegmo Son,Byungmin Kam,Yong Sang Joh,Sang-Joon Park,Won-Jun Lee,Jongwan Jung,Seongjae Cho +7 more
TL;DR: In this article, the authors investigated the reliability issues with respect to short-channel effects (SCEs) when targeting 10-nm and beyond logic technologies, and various emerging research devices with novel structures have been proposed to enhance gate controllability over the channel and to suppress the SCEs.
Journal ArticleDOI
Impact of Sidewall Spacer Materials and Gate Underlap Length on Negative Capacitance Double-Gate Tunnel Field-Effect Transistor (NCDG-TFET)
Seu-Youn Go,Shinhee Kim,Jae Yeon Park,Dong-Keun Lee,Hyung Ju Noh,So Ra Park,Yoon Kim,Dae Hwan Kim,Sangwan Kim +8 more
TL;DR: In this paper , a negative capacitance double-gate tunnel field effect transistor with sidewall spacer engineering is proposed and its electrical characteristics are examined by technology computer-aided design (TCAD) simulation for lower subthreshold swing (SS) and higher on-off current ratio ( I on / I off ).