Journal ArticleDOI
Fundamental Study of Complementary Metal Oxide Semiconductor Image Sensor for Three-Dimensional Image Processing System
Kenji Makita,K. Kiyoyama,Takeaki Sugimura,Kang-Wook Lee,Takafumi Fukushima,Tetsu Tanaka,Mitsumasa Koyanagi +6 more
TLDR
A fundamental study of a complementary metal oxide semiconductor (CMOS) image sensor for a three-dimensional (3D) image-processing system and a pixel circuit with correlated double sampling (CDS) and high-speed image capturing for high- speed image processing is proposed.Abstract:
In this paper, we describe a fundamental study of a complementary metal oxide semiconductor (CMOS) image sensor for a three-dimensional (3D) image-processing system. We proposed a pixel circuit with correlated double sampling (CDS) and high-speed image capturing for high-speed image processing. The CDS and high-speed image-capture circuit should be realized simultaneously to allow high-speed image processing. The pixel circuit can realize CDS and high-speed image-capture functions simultaneously. The CDS and high-speed image capturing are realized by using a pixel sample hold capacitor and shared coupling capacitor. Appending extra capacitors causes the pixel circuit size to become large in the two-dimensional (2D) CMOS image sensor. We proposed a 3D CMOS image sensor that can reduce the pixel circuit size and the electrical wiring length and increase the fill factor, even with CDS and high-speed image capturing. Therefore, small, high-speed parallel-processing systems can be realized by using our 3D CMOS image sensor. We fabricated the prototype 2D pixel circuit with CDS and high-speed image capturing. The prototype pixel circuit is successfully implemented in the simultaneous function. We believe the proposed pixel circuit is very effective for 3D CMOS image processing.read more
Citations
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Proceedings ArticleDOI
A very low area ADC for 3-D stacked CMOS image processing system
Koji Kiyoyama,K. W. Lee,Takafumi Fukushima,Hideki Naganuma,Harufumi Kobayashi,Tetsu Tanaka,Mitsumasa Koyanagi +6 more
TL;DR: A very small circuit area analog-to-digital converter (ADC) for three-dimensional (3-D) stacked CMOS image processing system and the time interleaved charge-redistribution successive approximation (SAR) method is employed.
Proceedings ArticleDOI
A parallel ADC for high-speed CMOS image processing system with 3D structure
K. Kiyoyama,Yoshikazu Ohara,K-W Lee,Y. Yang,Takafumi Fukushima,Tetsu Tanaka,Mitsumasa Koyanagi +6 more
TL;DR: The fundamental study of a parallel signal processing circuit, which includes a pixel circuit and a parallel analog-to-digital converter (ADC) with hierarchical correlated double sampling (CDS), with block-parallel signal processing with three-dimensional (3D) structure is described.
Proceedings ArticleDOI
Development of via-last 3D integration technologies using a new temporary adhesive system
TL;DR: New via-last backside-via 3D integration technologies using a unique temporary adhesive system in which visible-light laser is employed for wafer debonding from glass carriers are developed.
Journal ArticleDOI
Superior decoupling capacitor for three-dimensional LSI with ultrawide communication bus
Proceedings ArticleDOI
A block-parallel ADC with digital noise cancelling for 3-D stacked CMOS image sensor
Koji Kiyoyama,Yutaka S. Sato,Hideki Hashimoto,Kang-Wook Lee,Takafumi Fukushima,Tetsu Tanaka,Mitsumasa Koyanagi +6 more
TL;DR: The digital CDS proposed in this paper is used to eliminate FPN caused by the device variation of analog circuits in the high speed CMOS image sensor by using proposed hierarchical double CDS function.
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