GENIE: A Generalized Array Optimizer for VLSI Synthesis

TLDR: A new generalized array optimization scheme is presented which solves the problem of efficient automatic layout of multi-level CMOS and NMOS logic circuits and is implemented in the program GENIE, the first program to produce high-quality, automated SLA implementations.

Abstract: A new generalized array optimization scheme is presented which solves the problem of efficient automatic layout of multi-level CMOS and NMOS logic circuits. The new approach has been implemented in the program GENIE which can be used for the multiple folding of PLAs, as well as for compacting gate matrix layouts, SLAs, and Weinberger arrays. The cells in the array can be of non-uniform sizes and any form of constraint can be placed on the input and output terminals. The generalized array optimizer uses the combinatorial optimization technique called Simulated Annealing. Results obtained are uniformly better than existing specialized array optimizers and folding programs, particularly when the inputs locations are constrained. GENIE is the first program to produce high-quality, automated SLA implementations.