Proceedings ArticleDOI
How To Do Weighted Random Testing For Bist
J. Hartmann,G. Kemnitz +1 more
- Vol. 1993, pp 568-571
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TLDR
A strategy as proposed takes into account all aspects of wezghted random testzng for BIST, and examines the only random pattern resastant ISCAS 85 benchmarks c2670 and c7552 as an empiracal evaluation.Abstract:
In this paper, a strategy as proposed whach takes into account all aspects of wezghted random testzng for BIST. Our approach arwes from results concernzng the ampact of wezght roundang and a new combznataon of known technzques lake couplzng unweaghted and weighted pattern generatzon, basang weaght calculatzon on a precomputed test [2, 61, numerical maxzmazataon of pattern coverage [4], GURT-like hardware amplementatzon [lo], and avozdzng auto-correlataons. As an empiracal evaluation, we examzned the only random pattern resastant ISCAS 85 benchmarks c2670 and c7552. For these ctrcuats, 100% fault coverage was achieved after a total of 16,000 and 256,000 patterns, respectively. The hardware overhead compared to a pure random test as less than 2.5%.read more
Citations
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Proceedings ArticleDOI
Test point insertion based on path tracing
Nur A. Touba,Edward J. McCluskey +1 more
TL;DR: This paper presents an innovative method for inserting test points in the circuit-under-test to obtain complete fault coverage for a specified set of test patterns using a path tracing procedure.
Proceedings ArticleDOI
Synthesis of mapping logic for generating transformed pseudo-random patterns for BIST
Nur A. Touba,Edward J. McCluskey +1 more
TL;DR: It is shown that by performing iterative global operations, the procedure described in this paper generates mapping logic that requires less hardware overhead to achieve the same fault coverage for the same test length.
Proceedings ArticleDOI
Low hardware overhead scan based 3-weight weighted random BIST
TL;DR: Experimental results show that the proposed BIST schemes can attain 100% fault coverage for all of benchmark circuits with drastically reduced test sequence lengths, achieved at low hardware cost even for benchmark circuits that have large number scan inputs.
Proceedings ArticleDOI
A novel pattern generator for near-perfect fault-coverage
TL;DR: A new design methodology for a pattern generator is proposed, formulated in the context of on-chip BIST, which consists of a GLFSR and combinational logic, to snap the outputs of the pseudo-random pattern generator.
Proceedings ArticleDOI
Generation of low power dissipation and high fault coverage patterns for scan-based BIST
TL;DR: A low hardware overhead test pattern generator (TPG) for scan-based BIST that can reduce switching activity in CUTs during BIST and also achieve very high fault coverage with a reasonable length of test sequence is presented.
References
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Journal ArticleDOI
Random-pattern coverage enhancement and diagnosis for LSSD logic self-test
E. B. Eichelberger,E. Lindbloom +1 more
TL;DR: Embedded linear feedback shift registers can be used for logic component self-test and a procedure that supports net-level diagnosis for structured logic in the presence of random test-pattern generation and signature analysis is given.
Journal ArticleDOI
The Weighted Random Test-Pattern Generator
TL;DR: This paper presents a technique for generating statistically random sequences to test complex logic circuits and several techniques for assigning these weights and for varying them are discussed on the basis of the primary algorithm.
Proceedings ArticleDOI
A new procedure for weighted random built-in self-test
TL;DR: It is proposed that a pseudorandom sequence and a single weighted random sequence be used to implement built-in self-test (BIST) efficiently in a large integrated scan circuit which would otherwise need an excessive pseudo-random test length.
Self test using unequiprobable random patterns
TL;DR: A module generating unequiprobable random patterns, which can also perform signature analysis and work like a normal register similar to the well known BILBO is presented, which expands the class of self testable circuits without additional costs.
Proceedings ArticleDOI
Test set embedding in a built-in self-test environment
S.B. Akers,W. Jansz +1 more
TL;DR: The authors describe a built-in self-test (BIST) technique where the on-chip test pattern generator is a binary counter with associated XOR gates that forms the basis for the synthesis of the binary counter and accompanying (combinational) logic using linear algebraic techniques.