Journal ArticleDOI
Improvement of integrated circuit testing reliability by using the defect based approach
TLDR
It is shown that a stuck-at-fault-optimized test-vector set may prove highly inefficient in detecting spot-defect-induced faults, and a few methods are discussed that make the DBT less time consuming.About:
This article is published in Microelectronics Reliability.The article was published on 2003-06-01. It has received 12 citations till now. The article focuses on the topics: Automatic test pattern generation & Testing reliability.read more
Citations
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Journal ArticleDOI
Using intuitionistic fuzzy sets for fault-tree analysis on printed circuit board assembly
TL;DR: An algorithm of the intuitionistic fuzzy fault-tree analysis is proposed in this paper to calculate fault interval of system components and to find the most critical system component for the managerial decision-making based on some basic definitions.
Journal ArticleDOI
DefSim: A Remote Laboratory for Studying Physical Defects in CMOS Digital Circuits
TL;DR: A unique remote laboratory for studying CMOS physical defects that is meant to be used in advanced courses in the scope of microelectronic design and test and accessible over the Internet, thereby supporting distance learning and e-learning modes of training.
Proceedings ArticleDOI
Hierarchical Analysis of Short Defects between Metal Lines in CMOS IC
TL;DR: A new bridging fault simulator and a test pattern generator, which are able to handle defects creating feedbacks into the circuit, are introduced and shown how the number of bridging faults of non-zero probability is dependent on the circuit size.
Proceedings ArticleDOI
Characterization of CMOS sequential standard cells for defect based voltage testing
TL;DR: A new characterization methodology of CMOS sequential standard cells for defect based voltage testing is presented that allows to estimate the probabilities of physical defects occurrences in a cell, describes its faulty behavior caused by the defects and finds the test sequences that detect those faults.
Proceedings ArticleDOI
DefSim - the educational integrated circuit for defect simulation
TL;DR: The educational integrated circuit, DefSim, is described, dedicated to the development of students' skills in fault simulation and test pattern generation for digital circuits.
References
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Book
Digital Systems Testing and Testable Design
TL;DR: The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.
Book
Logic Testing and Design for Testability
TL;DR: This book is very referred for you because it gives not only the experience but also lesson, that will give wellness for all people from many societies.
Book
Defect and Fault Tolerance in Vlsi Systems
TL;DR: In this article, the authors present a unified approach to yield analysis of fault-free or fault-tolerant VLSI manufacturing, including the effect of defect density on yield.
Proceedings ArticleDOI
CMOS standard cells characterization for defect based testing
TL;DR: This paper extends the CMOS standard cells characterization methodology for defect based testing to find the types of faults which may occur in a real IC, to determine their probabilities, and to finding the input test vectors which detect these faults.