Proceedings ArticleDOI
Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers
Norman P. Jouppi
- Vol. 18, pp 364-373
TLDR
In this article, a hardware technique to improve the performance of caches is presented, where a small fully-associative cache between a cache and its refill path is used to place prefetched data and not in the cache.Abstract:
Projections of computer technology forecast processors with peak performance of 1,000 MIPS in the relatively near future. These processors could easily lose half or more of their performance in the memory hierarchy if the hierarchy design is based on conventional caching techniques. This paper presents hardware techniques to improve the performance of caches.Miss caching places a small fully-associative cache between a cache and its refill path. Misses in the cache that hit in the miss cache have only a one cycle miss penalty, as opposed to a many cycle miss penalty without the miss cache. Small miss caches of 2 to 5 entries are shown to be very effective in removing mapping conflict misses in first-level direct-mapped caches.Victim caching is an improvement to miss caching that loads the small fully-associative cache with the victim of a miss and not the requested line. Small victim caches of 1 to 5 entries are even more effective at removing conflict misses than miss caching.Stream buffers prefetch cache lines starting at a cache miss address. The prefetched data is placed in the buffer and not in the cache. Stream buffers are useful in removing capacity and compulsory cache misses, as well as some instruction cache conflict misses. Stream buffers are more effective than previously investigated prefetch techniques at using the next slower level in the memory hierarchy when it is pipelined. An extension to the basic stream buffer, called multi-way stream buffers, is introduced. Multi-way stream buffers are useful for prefetching along multiple intertwined data reference streams.Together, victim caches and stream buffers reduce the miss rate of the first level in the cache hierarchy by a factor of two to three on a set of six large benchmarks.read more
Citations
More filters
Patent
Method and apparatus for tracking processing of a command
TL;DR: In this article, a command directory includes a command buffer having a plurality of directory entries, which stores a command and associated status information in a directory entry, and a free buffer logic is used to monitor the status information.
Journal ArticleDOI
High bandwidth on-chip cache design
K.M. Wilson,Kunle Olukotun +1 more
TL;DR: The results show that a large dual-ported multicycle pipelined SRAM cache with a line buffer maximizes processor performance, which is both a low miss rate and a high CPU clock frequency.
Proceedings ArticleDOI
Reducing cache pollution of prefetching in a small data cache
TL;DR: Results from the simulations indicate that with the proposed technique, cache pollution can be reduced on a small set associative cache.
Patent
Method and apparatus for next-line prefetching from a predicted memory address
TL;DR: In this paper, a method and apparatus for issuing one or more next-line prefetch requests from a predicted memory address is presented, which corresponds to a cache line having a memory address contiguous with the predicted address.
Proceedings ArticleDOI
Increasing multicore system efficiency through intelligent bandwidth shifting
Victor Jimenez,Alper Buyuktosunoglu,Pradip Bose,Francis Patrick O'Connell,Francisco J. Cazorla,Mateo Valero +5 more
TL;DR: This paper proposes an online bandwidth shifting mechanism that dynamically assigns bandwidth to applications according to their prefetch efficiency, which maximizes the utilization of memory bandwidth, thereby improving system performance and/or reducing memory power consumption.
References
More filters
Journal ArticleDOI
Cache Memories
TL;DR: Specific aspects of cache memories investigated include: the cache fetch algorithm (demand versus prefetch), the placement and replacement algorithms, line size, store-through versus copy-back updating of main memory, cold-start versus warm-start miss ratios, mulhcache consistency, the effect of input /output through the cache, the behavior of split data/instruction caches, and cache size.
Why Aren't Operating Systems Getting Faster As Fast as Hardware?
TL;DR: This note evaluates several hardware platforms and operating systems using a set of benchmarks that test memory bandwidth and various operating system features such as kernel entry/exit and file systems to conclude that operating system performance does not seem to be improving at the same rate as the base speed of the underlying hardware.
Journal ArticleDOI
Available instruction-level parallelism for superscalar and superpipelined machines
Norman P. Jouppi,David W. Wall +1 more
TL;DR: A parameterizable code reorganization and simulation system was developed and used to measure instruction-level parallelism and the average degree of superpipelining metric is introduced, suggesting that this metric is already high for many machines.
Journal ArticleDOI
Sequential Program Prefetching in Memory Hierarchies
TL;DR: It is shown that prefetching all memory references in very fast computers can increase the effective CPU speed by 10 to 25 percent.
Proceedings ArticleDOI
On the inclusion properties for multi-level cache hierarchies
Jean-Loup Baer,Wen-Hann Wang +1 more
TL;DR: The inclusion property is essential in reducing the cache coherence complexity for multiprocessors with multilevel cache hierarchies and a new inclusion-coherence mechanism for two-level bus-based architectures is proposed.