Proceedings ArticleDOI
Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers
Norman P. Jouppi
- Vol. 18, pp 364-373
TLDR
In this article, a hardware technique to improve the performance of caches is presented, where a small fully-associative cache between a cache and its refill path is used to place prefetched data and not in the cache.Abstract:
Projections of computer technology forecast processors with peak performance of 1,000 MIPS in the relatively near future. These processors could easily lose half or more of their performance in the memory hierarchy if the hierarchy design is based on conventional caching techniques. This paper presents hardware techniques to improve the performance of caches.Miss caching places a small fully-associative cache between a cache and its refill path. Misses in the cache that hit in the miss cache have only a one cycle miss penalty, as opposed to a many cycle miss penalty without the miss cache. Small miss caches of 2 to 5 entries are shown to be very effective in removing mapping conflict misses in first-level direct-mapped caches.Victim caching is an improvement to miss caching that loads the small fully-associative cache with the victim of a miss and not the requested line. Small victim caches of 1 to 5 entries are even more effective at removing conflict misses than miss caching.Stream buffers prefetch cache lines starting at a cache miss address. The prefetched data is placed in the buffer and not in the cache. Stream buffers are useful in removing capacity and compulsory cache misses, as well as some instruction cache conflict misses. Stream buffers are more effective than previously investigated prefetch techniques at using the next slower level in the memory hierarchy when it is pipelined. An extension to the basic stream buffer, called multi-way stream buffers, is introduced. Multi-way stream buffers are useful for prefetching along multiple intertwined data reference streams.Together, victim caches and stream buffers reduce the miss rate of the first level in the cache hierarchy by a factor of two to three on a set of six large benchmarks.read more
Citations
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Journal ArticleDOI
Victim management in a cache hierarchy
TL;DR: It is shown that pattern locality information, based on discard statistics, can be useful in enhancing the quality of prefetch decisions, as well as the maintenance of information on the current location of discarded lines.
Book ChapterDOI
HBM-Resident Prefetching for Heterogeneous Memory System
TL;DR: It is shown that, reserving a small fraction of HBM memory to host a hardware prefetch buffer can improve IPC for a set of SPEC CPU2006 and HPC benchmarks by an average of 34% and a maximum of 98% over a baseline system with no-prefetching.
Proceedings ArticleDOI
Extended histories: improving regularity and performance in correlation prefetchers
TL;DR: It is demonstrated that extending the training information to include secondary misses and hits along with primary misses helps improve the performance of prefetchers, and the information theoretic metric entropy is used, to quantify the regularity present in extended histories.
Proceedings ArticleDOI
CAMPS: Conflict-Aware Memory-Side Prefetching Scheme for Hybrid Memory Cube
Muhammad M. Rafique,Zhichun Zhu +1 more
TL;DR: A memory-side prefetching scheme for HMC based main memory system that utilizes its logic area and exploits the huge internal bandwidth provided by TSVs and a prefetch buffer management scheme that makes replacement decision within the prefetchbuffer based on both the utilization and recency of the prefetched rows.
Proceedings ArticleDOI
Improving the Effectiveness of Context-Based Prefetching with Multi-order Analysis
TL;DR: The simulation results show that the proposed MOC prefetching method outperforms the existing single-order prefetchy and reduces the data-access latency effectively, and motivated by the observations from the analytical results, proposes a new context-based prefetched method named Multi-Order Context-based (MOC) prefetchers to adopt multi-order context analysis.
References
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Journal ArticleDOI
Cache Memories
TL;DR: Specific aspects of cache memories investigated include: the cache fetch algorithm (demand versus prefetch), the placement and replacement algorithms, line size, store-through versus copy-back updating of main memory, cold-start versus warm-start miss ratios, mulhcache consistency, the effect of input /output through the cache, the behavior of split data/instruction caches, and cache size.
Why Aren't Operating Systems Getting Faster As Fast as Hardware?
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Journal ArticleDOI
Available instruction-level parallelism for superscalar and superpipelined machines
Norman P. Jouppi,David W. Wall +1 more
TL;DR: A parameterizable code reorganization and simulation system was developed and used to measure instruction-level parallelism and the average degree of superpipelining metric is introduced, suggesting that this metric is already high for many machines.
Journal ArticleDOI
Sequential Program Prefetching in Memory Hierarchies
TL;DR: It is shown that prefetching all memory references in very fast computers can increase the effective CPU speed by 10 to 25 percent.
Proceedings ArticleDOI
On the inclusion properties for multi-level cache hierarchies
Jean-Loup Baer,Wen-Hann Wang +1 more
TL;DR: The inclusion property is essential in reducing the cache coherence complexity for multiprocessors with multilevel cache hierarchies and a new inclusion-coherence mechanism for two-level bus-based architectures is proposed.