Proceedings ArticleDOI
Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers
Norman P. Jouppi
- Vol. 18, pp 364-373
TLDR
In this article, a hardware technique to improve the performance of caches is presented, where a small fully-associative cache between a cache and its refill path is used to place prefetched data and not in the cache.Abstract:
Projections of computer technology forecast processors with peak performance of 1,000 MIPS in the relatively near future. These processors could easily lose half or more of their performance in the memory hierarchy if the hierarchy design is based on conventional caching techniques. This paper presents hardware techniques to improve the performance of caches.Miss caching places a small fully-associative cache between a cache and its refill path. Misses in the cache that hit in the miss cache have only a one cycle miss penalty, as opposed to a many cycle miss penalty without the miss cache. Small miss caches of 2 to 5 entries are shown to be very effective in removing mapping conflict misses in first-level direct-mapped caches.Victim caching is an improvement to miss caching that loads the small fully-associative cache with the victim of a miss and not the requested line. Small victim caches of 1 to 5 entries are even more effective at removing conflict misses than miss caching.Stream buffers prefetch cache lines starting at a cache miss address. The prefetched data is placed in the buffer and not in the cache. Stream buffers are useful in removing capacity and compulsory cache misses, as well as some instruction cache conflict misses. Stream buffers are more effective than previously investigated prefetch techniques at using the next slower level in the memory hierarchy when it is pipelined. An extension to the basic stream buffer, called multi-way stream buffers, is introduced. Multi-way stream buffers are useful for prefetching along multiple intertwined data reference streams.Together, victim caches and stream buffers reduce the miss rate of the first level in the cache hierarchy by a factor of two to three on a set of six large benchmarks.read more
Citations
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Tools and techniques for memory system design and analysis
TL;DR: In this paper, the authors present an interface for writing memory system simulators, called active memory abstraction, designed specifically for simulators that process memory references as the application executes and avoid storing them to tape or disk.
Proceedings ArticleDOI
Hiding cache miss penalty using priority-based execution for embedded processors
TL;DR: This paper proposes a hardware-software cooperative approach, called priority-based execution to hide cache miss penalty for embedded processors, and empirically evaluates the proposal on the Intel XScale compiler and microarchitecture.
Proceedings ArticleDOI
The Cache-Core Architecture to Enhance the Memory Performance on Multi-Core Processors
Yosuke Mori,Kenji Kise +1 more
TL;DR: The Cache-Core is a mechanism where the excess core behaves like an L2 data cache by executing software managed cache program, where the number of global memory accesses can decrease, and the Cache- Core enhances the performance of multi-core processor.
Book ChapterDOI
Compiler-Directed Cache Assist Adaptivity
TL;DR: The results show that a cache assist that is adaptive at loop level clearly improves the cache memory performance, has low overhead, and can be easily implemented.
Journal ArticleDOI
Speculative execution for hiding memory latency
TL;DR: This paper presents a mechanism to speculatively execute independent instructions of L2-miss loads, even if no entry in the reorder buffer is available, which obtains 21% of performance improvement.
References
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Journal ArticleDOI
Cache Memories
TL;DR: Specific aspects of cache memories investigated include: the cache fetch algorithm (demand versus prefetch), the placement and replacement algorithms, line size, store-through versus copy-back updating of main memory, cold-start versus warm-start miss ratios, mulhcache consistency, the effect of input /output through the cache, the behavior of split data/instruction caches, and cache size.
Why Aren't Operating Systems Getting Faster As Fast as Hardware?
TL;DR: This note evaluates several hardware platforms and operating systems using a set of benchmarks that test memory bandwidth and various operating system features such as kernel entry/exit and file systems to conclude that operating system performance does not seem to be improving at the same rate as the base speed of the underlying hardware.
Journal ArticleDOI
Available instruction-level parallelism for superscalar and superpipelined machines
Norman P. Jouppi,David W. Wall +1 more
TL;DR: A parameterizable code reorganization and simulation system was developed and used to measure instruction-level parallelism and the average degree of superpipelining metric is introduced, suggesting that this metric is already high for many machines.
Journal ArticleDOI
Sequential Program Prefetching in Memory Hierarchies
TL;DR: It is shown that prefetching all memory references in very fast computers can increase the effective CPU speed by 10 to 25 percent.
Proceedings ArticleDOI
On the inclusion properties for multi-level cache hierarchies
Jean-Loup Baer,Wen-Hann Wang +1 more
TL;DR: The inclusion property is essential in reducing the cache coherence complexity for multiprocessors with multilevel cache hierarchies and a new inclusion-coherence mechanism for two-level bus-based architectures is proposed.