Proceedings ArticleDOI
Low power, low voltage, 10bit-50MSPS pipeline ADC dedicated for front-end ultrasonic receivers
Kamal El-Sankary,Abdallah Kassem,Robert Chebli,M. Sawan +3 more
- pp 219-222
TLDR
The design and the implementation of a low power, low voltage 10bit-50MS/s pipeline analog to digital converter (ADC) dedicated to ultrasonic receivers and a digital offset compensation to relax the constraints on the analog circuitry is proposed.Abstract:
This paper concerns the design and the implementation of a low power, low voltage 10bit-50MS/s pipeline analog to digital converter (ADC) dedicated to ultrasonic receivers The ADC is used in the front-end stage to convert the signals coming from the time gain compensator (TGC) of the handheld ultrasonic apparatus The proposed architecture is based on 15 bits per stage pipeline structure followed by a digital offset compensation to relax the constraints on the analog circuitry The converter is implemented in digital CMOS 018 /spl mu/m technology, the circuit occupies an active area of 12 mm/sup 2/, the input differential voltage dynamic range is chosen to be 16 Vpp and the power consumption is found to be 31 mW from 18 V supplyread more
Citations
More filters
Journal ArticleDOI
Ultra-low power transmit/receive ASIC for battery operated ultrasound measurement systems
TL;DR: In this article, the authors describe the design of the complete transmit and receive electronics circuitry for a piezoelectric transducer in one single ASIC, which is used as one building block in a thumb size battery operated ultrasound measurement system.
Journal ArticleDOI
A Survey on Analog-to-Digital Converter Integrated Circuits for Miniaturized High Resolution Ultrasonic Imaging System
TL;DR: The architecture and performance of ADC for UIS, including successive approximation register (SAR), sigma-delta (Σ-∆) ADC, pipelined ADC, and hybrid ADC, have been systematically introduced.
Proceedings ArticleDOI
Optimization of bit-per-stage for low-voltage low-power CMOS pipeline ADCs
TL;DR: The results of the optimization analysis show that 2.5 bit-per-stage is the optimum for the 10-bit ADC design with digital error correction, and can be generalized for any n-bit low-voltage pipeline ADC.
Proceedings ArticleDOI
High resolution self-calibrated ADCs for software defined radios
Kamal El-Sankary,Mohamad Sawan +1 more
TL;DR: Methods to overcome the technology limitations are presented to achieve high linearity without compromising the low power consumption of the wide-bandwidth transceivers.
Proceedings ArticleDOI
Pipelined sampled-delay focusing CMOS implementation for ultrasonic digital beamforming
TL;DR: The design and implementation of pipelined sampled-delay architecture for ultrasonic digital beamforming uses a minimum size look-up memory to store the initial scan information as opposed to previous approaches.
References
More filters
Journal ArticleDOI
A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter
A.M. Abo,Paul R. Gray +1 more
TL;DR: In this paper, a 1.5-V, 10-bit, 14.3-MS/s pipeline analog-to-digital converter was implemented in a 0.6/spl mu/m CMOS technology.
Proceedings ArticleDOI
Logarithmic programmable preamplifier dedicated to ultrasonic receivers
TL;DR: The design, the implementation and the validation of a fully integrated preamplifier dedicated to ultrasonic receivers and a programmable-gain module built around a Timing Gain Compensator (TGC) are concerns.
Proceedings ArticleDOI
A 115mW 12-bit 50 MSPS pipelined ADC
Sumeet Mathur,M. Das,Preetam Charan Anand Tadeparthy,S. Ray,Subhashish Mukherjee,B.L. Dinakaran +5 more
TL;DR: This paper presents a low power pipelined ADC cell implemented in a 0.18 /spl mu/m digital CMOS process that achieves -70dB THD performance for 10 MHz input at 50 MHz sampling rate.
Journal ArticleDOI
Design and power optimization of high-speed pipeline ADC for wideband CDMA applications
TL;DR: In this article, a 7-bit 64 MS/s pipeline A/D converter for wideband CDMA applications is presented, aiming at achieving low power dissipation at high speed, techniques such as digital correction and optimal scaling of capacitor value have been employed to further reduce power consumption.