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Journal ArticleDOI

Low-Power Scan Operation in Test Compression Environment

TLDR
A new on-chip continuous-flow decompressor that integrates seamlessly with test logic synthesis flow, and it fits well into various design paradigms, including modular design flow where blocks come with individual decompressors and compactors.
Abstract
This paper presents a new and comprehensive low-power test scheme compatible with a test compression environment. The key contribution of this paper is a flexible test-application framework that achieves significant reductions in switching activity during all phases of scan test: loading, capture, and unloading. In particular, we introduce a new on-chip continuous-flow decompressor. Its synergistic use with a power-aware scan controller allows a significant reduction of toggling rates when feeding scan chains with decompressed test patterns. While the proposed solution requires minimal modifications of the existing design for test logic, experiments indicate that its use results in a low switching activity which reduces power consumption to or below a level of a functional mode. It resolves problems related to power dissipation, voltage drop, and increased temperature. Our approach integrates seamlessly with test logic synthesis flow, and it does not compromise compression ratios. It fits well into various design paradigms, including modular design flow where blocks come with individual decompressors and compactors.

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Citations
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Journal ArticleDOI

Deterministic Clustering of Incompatible Test Cubes for Higher Power-Aware EDT Compression

TL;DR: It is demonstrated that compression ratios can be order of magnitude higher, if the cube merging continues despite conflicts on certain positions, and that test clusters make it possible to deliver test patterns in a flexible power-aware fashion.
Proceedings ArticleDOI

Functional test of small-delay faults using SAT and Craig interpolation

TL;DR: SATSEQ is presented, a timing-aware ATPG system for small-delay faults in non-scan circuits that provides detection of small- delay faults through the longest functional paths and generates the shortest possible sub-sequences per fault.
Proceedings ArticleDOI

Low power compression of incompatible test cubes

TL;DR: A flexible test application framework that achieves significant reductions in switching activity during scan loading by means of a tri-modal test data decompressor is presented.
Proceedings ArticleDOI

Continuous process monitoring for biogas plants using microwave sensors

TL;DR: In this article, the authors used microwave sensors to measure the dry matter content of biogas during anaerobic digestion, and the setup of the measuring system for materials with high water content was presented.
References
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Proceedings ArticleDOI

A distributed BIST control scheme for complex VLSI devices

TL;DR: A BIST scheduling process that takes into consideration constraints is presented, and a new BIST control methodology is introduced, that implements the BIST schedule with a highly modular architecture.
Journal ArticleDOI

Embedded deterministic test

TL;DR: This paper presents a novel test-data volume-compression methodology called the embedded deterministic test (EDT), which reduces manufacturing test cost by providing one to two orders of magnitude reduction in scan test data volume and scan test time.
Journal ArticleDOI

Survey of Test Vector Compression Techniques

TL;DR: This article summarizes and categories hardware-based test vector compression techniques for scan architectures, which fall broadly into three categories: code-based schemes use data compression codes to encode test cubes; linear-decompression- based schemes decompress the data using only linear operations; and broadcast-scan-based scheme rely on broadcasting the same values to multiple scan chains.
Proceedings ArticleDOI

Static compaction techniques to control scan vector power dissipation

TL;DR: It is shown here that by carefully selecting the order in which pairs of test cubes are merged during static compaction, both average power and peak power for the final test set can be greatly reduced.
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