Journal ArticleDOI
Mask characterization for double patterning lithography
TLDR
The performance of a two-reticle set based on a design developed to study the impact of global and local mask placement errors on double patterning using a dual-line process is reported on.Abstract:
Double patterning (DPT) lithography is seen industry-wide as an intermediate solution for the 32-nm node if high index immersion as well as extreme ultraviolet lithography are not ready for a timely release for production. Apart from the obvious drawbacks of the additional exposure, the processing steps, and the resulting reduced throughput, DPT possesses a number of additional technical challenges. This relates to, e.g., exposure tool capability, the actual applied process in the wafer fab, but also to mask performance and metrology. In this work we address the mask performance. To characterize the mask performance in an actual DPT process, conventional mask parameters need to be re-evaluated. Furthermore, new parameters might be more suitable to describe mask capability. This refers to, e.g., reticle to reticle overlay, but also to CD differences between masks of a DPT reticle set. For the 32-nm node, a DPT target of reticle to reticle induced overlay of 6 nm, 3 at mask level, was recently proposed. We report on the performance of a two-reticle set based on a design developed to study the impact of global and local mask placement errors on double patterning using a dual-line process. In a first step we focus on reticle to reticle overlay based on conventional mask metrology. The overlay between two masks evaluated for standard wafer overlay targets is compared with measurements on actual resolution structures, contributions of displacements on different spatial scales are discussed, and mask to mask CD variations are addressed. In a second step, we compare reticle data with experimental intrafield overlay data obtained from wafers on an ASML XT:1700i using the IMEC dual-line double patterning process. Reticle to reticle overlay contribution is studied on the wafers for both standard overlay targets and dedicated DPT features. The results of this study show...read more
Citations
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Patent
Tool and method for eliminating multi-patterning conflicts
Hung Lung Lin,Chin-Chang Hsu,Ying-Yu Shen,Wen-Ju Yang,Hsiao-Shu Chao,Yi-Kan Cheng,Chin-Hsiung Hsu,Huang-Yu Chen,Yi-Chuin Tsai,Yuan-Te Hou,Wang Chung-Hsing +10 more
TL;DR: In this paper, a computer implemented system comprises: a tangible, non-transitory computer readable storage medium encoded with data representing an initial layout of an integrated circuit pattern layer having a plurality of polygons.
Patent
Multi-patterning method
TL;DR: In this article, the layout of a DPT-layer of an integrated circuit generated by a place and route tool is represented by a plurality of polygons to be formed in the DPTlayer by a multi-patterning process.
PatentDOI
Single-mask double-patterning lithography
Puneet Gupta,Rani S. Ghaida +1 more
TL;DR: In this paper, a method of printing a final layout on a wafer comprises printing a first pattern from a first mask located at a first position onto the wafer, shifting the first mask by a predetermined distance to a second position, and applying a trim mask to the Wafer.
Patent
Routing system and method for double patterning technology
Huang-Yu Chen,Yuan-Te Hou,Gwan Sin Chang,Wen-Ju Yang,Zhe-Wei Jiang,Yi-Kan Cheng,Lee-Chung Lu +6 more
TL;DR: In this article, the first pattern has a plurality of segments and at least two of the segments have lengthwise directions perpendicular to each other, at least one pattern-free region is reserved adjacent to the first two segments, and none of the additional patterns is formed in the pattern free region.
Journal ArticleDOI
Single-Mask Double-Patterning Lithography for Reduced Cost and Improved Overlay Control
TL;DR: In this article, a shift-trim double-patterning lithography (ST-DPL) technique was proposed for achieving pitch relaxation with a single photomask, where the mask is re-used for the second exposure by applying a translational mask-shift.
References
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Proceedings ArticleDOI
Pitch doubling through dual-patterning lithography challenges in integration and litho budgets
Mircea Dusa,John Quaedackers,Olaf F. A. Larsen,Jeroen Meessen,Eddy van der Heijden,Gerald Dicker,Onno Wismans,Paul de Haas,Koen van Ingen Schenau,Jo Finders,Bert Vleeming,Geert Storms,Patrick Jaenen,Shaunee Cheng,Mireille Maenhoudt +14 more
TL;DR: A new CDU model was introduced to calculate double patterning budgets based on defining CD from its edges and pooling CD variance from two adjacent patterns within 2*Pitch distance, which achieved an experimental resolution of 32-nm 1/2 pitch on 1.2NA lithography system.
Proceedings ArticleDOI
Issues and challenges of double patterning lithography in DRAM
Seo-Min Kim,Sunyoung Koo,Jaeseung Choi,Young-Sun Hwang,Jungwoo Park,Eung-Kil Kang,Chang-Moon Lim,Seung-Chan Moon,Jinwoong Kim +8 more
TL;DR: 37nm DRAM layout can be patterned and the overlay control and cost still remain as dominant obstacles, and the aggressive layout decomposition should be designed to solve the difficulty in core patterning.
Proceedings ArticleDOI
Patterning with amorphous carbon spacer for expanding the resolution limit of current lithography tool
Wooyung Jung,Sang Min Kim,Choi-Dong Kim,Guee-Hwang Sim,Sung-Min Jeon,Sang Wook Park,Byung-Seok Lee,Sungki Park,Jisoo Kim,Lee-Sang Heon +9 more
TL;DR: In this article, negative type-double pattering technique using spacer has been developed as the best way for the application of NAND flash memory device from the view point of CD uniformity and the number of mask layers used to complete double patterning.
Proceedings ArticleDOI
Double patterning scheme for sub-0.25 k1 single damascene structures at NA=0.75, λ=193nm
TL;DR: In this paper, a double patterning scheme has been developed to obtain electrical structures at pitches from 140nm down to 100nm, which corresponds to k 1-factors of 0.27 to 0.19 for dense trenches.
Proceedings ArticleDOI
Positive and negative tone double patterning lithography for 50nm flash memory
Chang-Moon Lim,Seo-Min Kim,Young-Sun Hwang,Jaeseung Choi,Keundo Ban,Sung-Yoon Cho,Jin-Ki Jung,Eung-Kil Kang,Hee-Youl Lim,Hyeong-Soo Kim,Seung-Chan Moon +10 more
TL;DR: In this article, various issues in double patterning lithography such as pattern decomposition, resist process on patterned topography, process window of 1/4 pitch patterning, and overlay dependent CD variation are studied on positive and negative tone double patterns respectively.