Proceedings ArticleDOI
MNFTL: an efficient flash translation layer for MLC NAND flash memory storage systems
Zhiwei Qin,Yi Wang,Duo Liu,Zili Shao,Yong Guan +4 more
- pp 17-22
TLDR
This paper proposes two approaches, namely, concentrated mapping and postponed reclamation, to effective reduce the valid page copies in the design of MLC flash translation layer to reduce the garbage collection overhead.Abstract:
The new write constraints of multi-level cell (MLC) NAND flash memory make most of the existing flash translation layer (FTL) schemes inefficient or inapplicable. In this paper, we solve several fundamental problems in the design of MLC flash translation layer. The objective is to reduce the garbage collection overhead so as to reduce the average system response time. We make the key observation that the valid page copy is the essential garbage collection overhead. Based on this observation, we propose two approaches, namely, concentrated mapping and postponed reclamation, to effective reduce the valid page copies. We conduct experiments on a set of benchmarks from both the real world and synthetic traces. The experimental results show that our scheme can achieve a significant reduction in the average system response time compared with the previous work.read more
Citations
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Journal ArticleDOI
Survey of Techniques and Architectures for Designing Energy-Efficient Data Centers
Junaid Shuja,Kashif Bilal,Sajjad A. Madani,Mazliza Othman,Rajiv Ranjan,Pavan Balaji,Samee U. Khan +6 more
TL;DR: This paper presents the concept of inception of data center energy-efficiency controller that can consolidate data center resources with minimal effect on QoS requirements, and discusses software- and hardware-based techniques and architectures that can be manipulated by the data center controller to achieve energy efficiency.
Journal ArticleDOI
A survey of address translation technologies for flash memories
TL;DR: This survey focuses on address translation technologies and provides a broad overview of existing schemes described in patents, journals, and conference proceedings.
Posted Content
Errors in Flash-Memory-Based Solid-State Drives: Analysis, Mitigation, and Recovery
TL;DR: This chapter describes several mitigation and recovery techniques, including cell-tocell interference mitigation; optimal multi-level cell sensing; error correction using state-of-the-art algorithms and methods; and data recovery when error correction fails.
Journal ArticleDOI
DIDACache: An Integration of Device and Application for Flash-based Key-value Caching
TL;DR: This paper advocates to reconsider the cache system design and directly open device-level details of the underlying flash storage for key-value caching and implements a prototype, called DIDACache, based on the Open-Channel SSD platform.
Proceedings ArticleDOI
PCM-FTL: A Write-Activity-Aware NAND Flash Memory Management Scheme for PCM-Based Embedded Systems
TL;DR: This work presents for the first time a write-activity-aware Nander flash memory management scheme, called PCM-FTL, to effectively manage NAND flash memory and enhance the endurance of PCM -based embedded systems.
References
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Patent
Flash file system
TL;DR: The provision of a flash memory (12), virtual mapping system, which includes a flash controller (14) and a random access memory (16) for storing mapping tables, that allows data to be continuously written to unwritten physical address locations, is discussed in this paper.
Proceedings ArticleDOI
DFTL: a flash translation layer employing demand-based selective caching of page-level address mappings
TL;DR: This work proposes a complete paradigm shift in the design of the core FTL engine from the existing techniques with a Demand-based Flash Translation Layer (DFTL), which selectively caches page-level address mappings and develops a flash simulation framework called FlashSim.
Journal ArticleDOI
A log buffer-based flash translation layer using fully-associative sector translation
TL;DR: There is much room for performance improvement in the log buffer block scheme, and an enhanced log block buffer scheme, called FAST (full associative sector translation), is proposed, which improves the space utilization of log blocks using fully-associative sector translations for the log block sectors.
PostMark: A New File System Benchmark
TL;DR: Network Appliance Filers (file server appliances) are shown to provide superior performance (via NFS or CIFS) compared to local disk alternatives, especially at higher loads.
Proceedings ArticleDOI
A superblock-based flash translation layer for NAND flash memory
TL;DR: A novel superblockbased FTL scheme, which combines a set of adjacent logical blocks into a superblock, which decreases the garbage collection overhead up to 40% compared to previous FTL schemes.