Proceedings ArticleDOI
Modeling the unknown! Towards model-independent fault and error diagnosis
V. Boppana,M. Fujita +1 more
- pp 1094-1101
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TLDR
A technique for capturing the effects of all possible faulty behaviors that can be generated from specific sets of nodes (called X-lists) in the circuit is presented, which provides a way for drawing powerful diagnostic inferences about the presence of faults when analyzing the observed faulty responses.Abstract:
In this paper, we provide techniques for fault and error diagnosis based on capturing unmodeled faulty behavior. We present a technique for capturing the effects of all possible faulty behaviors that can be generated from specific sets of nodes (called X-lists) in the circuit. Since all possible erroneous behaviors are captured, this provides a way for drawing powerful diagnostic inferences about the presence of faults at these sets of nodes when analyzing the observed faulty responses. We also present an efficient diagnosis algorithm that exploits the modeling of all possible behaviors and can be built in a framework of conventional test and simulation tools. Experimental results with numerous diagnosis experiments are then used to demonstrate that the techniques developed can indeed be used to achieve significant improvements in the accuracy of diagnosis.read more
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Proceedings ArticleDOI
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Adaptive Debug and Diagnosis Without Fault Dictionaries
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References
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Proceedings ArticleDOI
HITEC: a test generation package for sequential circuits
TL;DR: HITEC is presented, a sequential circuit test generation package to generate test patterns for sequential circuits, without assuming the use of scan techniques or a reset state, and several new techniques are introduced to improve the performance of test generation.
Journal ArticleDOI
Failure diagnosis of structured VLSI
J.A. Waicukauski,E. Lindbloom +1 more
TL;DR: The authors describe a method for diagnosing the failures observed in testing VLSI designs that use the scan-path structure by simulating selected faults after testing using a fault simulator that allows the application of several patterns in parallel.
Proceedings ArticleDOI
Diagnosing CMOS bridging faults with stuck-at fault dictionaries
TL;DR: It is shown that the traditional approach to diagnosing stuck-at faults with fault dictionaries generated for stuck- at faults is not appropriate for diagnosing CMOS bridging faults, and a novel technique for using stuck-At-fault dictionaries to diagnose bridging fault diagnostic ability is described.
Journal ArticleDOI
A method of fault analysis for test generation and fault diagnosis
H. Cox,Janusz Rajski +1 more
TL;DR: The authors present a fault coverage analysis method for test generation and fault diagnosis of large combinational circuits using a 16-valued logic system, GEMINI, and an extended fault model which includes stuck-at, stuck-open, and delay faults is used.
Journal ArticleDOI
Multiple Fault Diagnosis in Combinational Circuits Based on an Effect-Cause Analysis
Abramovici,Breuer +1 more
TL;DR: The main vehicle of this approach is the deduction of internal line values in a circuit under test N*.