Multi-objective Optimization of Placement and Assignment of TSVs in 3D ICs
01 Jan 2017-pp 372-377
TL;DR: Although this method has some similarity with the framework of NSGA-II, several variations have been incorporated so that, on exploration of variety of non-dominated solutions the search process converges to a near-optimum solution in reasonable time.
Abstract: The advent of 3D IC technology facilitates fabrication of large logic circuits on low area yet high performance chips. For a 3D IC, placement followed by assignment of Through-Silicon-Vias (TSV)s is a challenging problem involving various issues like inter-layer wirelength, power density, congestion and variation in surrounding carrier mobility. Each of the existing techniques for placement of TSVs deals only with a subset of these issues. In this paper, we propose an evolutionary approach MO_TSV to handle this multi-objective optimization problem. Although this method has some similarity with the framework of NSGA-II, several variations have been incorporated so that, on exploration of variety of non-dominated solutions the search process converges to a near-optimum solution in reasonable time. Experimental results on ISCAS'85 and ISCAS'89 benchmarks yield solution quality aswell as convergence times, which are encouraging.
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TL;DR: This paper shows that the thermal impact on 3D processors is manageable by adopting thermal-aware techniques, thus making3D processors into the mainstream in the near future.
Abstract: Interconnect scaling has become a major design challenge for traditional planar (2D) integrated circuits (ICs). Three-dimensional (3D) IC that stacks multiple device layers through 3D stacking technology is regarded as an effective solution to this dilemma. A promising 3D IC design direction is to construct 3D processors. However, 3D processors are likely to suffer from more serious thermal issues as compared to conventional 2D processors, which may hinder the employment or even offset the benefits of 3D stacking. Therefore, thermal-aware design techniques should be adopted to alleviate the thermal problems with 3D processors. In this survey, we review works on system level optimization techniques for thermal-aware 3D processor design from hierarchical perspectives of architecture, floorplanning, memory management, and task scheduling. We first survey 3D processor architectures to demonstrate how a 3D processor can be constructed by using 3D stacking technology, and present an overview of thermal characteristics of the constructed 3D processors. We then review thermal-aware floorplanning, memory management and task scheduling techniques to show how the thermal impact on 3D processor performance can be reduced. A systematic classification method is utilized throughout the survey to emphasize similarities and differences of various thermal-aware 3D processor optimization techniques. This paper shows that the thermal impact on 3D processors is manageable by adopting thermal-aware techniques, thus making 3D processors into the mainstream in the near future.
72 citations
TL;DR: The proposed energy/thermal aware task scheduling approach can reduce more temperature by up to about 12∘C (depending on the specific application and related parameters) while keeping a competitive energy consumption compared with the state-of-the-arts.
Abstract: The energy issue of real-time applications with precedence-constrained tasks on heterogeneous systems has been studied recently. With the strikingly increasing power density due to the soaring system integration level, severe thermal issues arise which can in turn further aggravate the energy issues due to the strong temperature/leakage dependency. Any optimization should be insufficient if such dependency is not properly addressed. However, the state-of-the-art approaches either treat leakage power as a constant, or only adopt the dynamic power consumption as the heuristic metric to conduct the optimization, both of which cannot fully explore the optimization room for the two issues. To this end, we design an energy/thermal aware task scheduling approach by taking both the thermal and energy factors into consideration. The optimization is conducted from two aspects: first balance the energy/thermal loads of processors by assigning tasks in an energy/thermal aware heuristic way, and that of tasks by the deduced task-level deadlines; then reduce the waiting time between parallel tasks that share the same successor task. Extensive experiments conducted on real-world applications show that, the proposed approach can reduce more temperature by up to about 12∘C (depending on the specific application and related parameters) while keeping a competitive energy consumption compared with the state-of-the-arts.
21 citations
TL;DR: This paper proposes an evolutionary computation approach to handle the problem of placement followed by the assignment of through-silicon vias of 3-D ICs in a novel way so that, on exploration of a variety of nondominated solutions, the search process converges to a near-optimum solution in reasonable time.
Abstract: The advent of 3-D IC technology facilitates the fabrication of large electronic circuits on small-area chips ensuring high performance. For a 3-D IC, the problem of placement followed by the assignment of through-silicon vias (TSVs) involves optimizing various design objectives such as intertier wirelength, power density, congestion, and separation between the TSVs. Each of the existing techniques for the placement of TSVs deals only with a subset of these objectives. In this paper, we propose an evolutionary computation approach $MO\_{}TSV$ to handle this multiobjective optimization problem. The operators, parameters, and constituents of the framework of genetic algorithm (GA)-based multiobjective optimization have been designed in a novel way so that, on exploration of a variety of nondominated solutions, the search process converges to a near-optimum solution in reasonable time. Experimental results on ISCAS’85, ISCAS’89, ITC’99, and IBM (ISPD’98) benchmarks yield quality solutions in terms of all the parameters as well as convergence times, which are encouraging.
6 citations
Cites methods from "Multi-objective Optimization of Pla..."
...A preliminary version of the proposed technique was in [4]....
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01 Nov 2018
TL;DR: In this paper, a method to minimize resources of power distribution networks (PDNs) in a three-dimensional integrated circuit (3D IC) under the given design constraints is proposed.
Abstract: In this paper, we propose a method to minimize resources of power distribution networks (PDNs) in a three-dimensional integrated circuit (3D IC) under the given design constraints. We first present modeling of PDNs with RC reduction. Next, we describe the optimization of PDN parameters using a multi-objective optimization algorithm. The decoupling capacitors, on-chip power/ground grids, and power/ground through-silicon vias (TSVs), which have a great influence on the voltage drop (IR drop) and on the chip area increase, are optimized. The experimental results demonstrate that the new proposed method is effective for designing PDNs in 3D ICs.
3 citations
Cites methods from "Multi-objective Optimization of Pla..."
...TSV placement [12], floor planning [13], and PDN parameter optimization [14] using a non-dominated sorting genetic algorithm (NSGA-II) [15-17] have been proposed....
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...However, the methods in [7-13] focus on the optimization of one physical parameter such as decoupling capacitors, power grids, and TSVs....
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01 Oct 2018
TL;DR: The results show with scaling from 45nm to 22 nm.
Abstract: We analyze the impact of through-silicon vias (TSVs) downsizing and future CMOS nanotechnology scaling on interconnect delay and power in 3-dimensional integrated circuits (3DICs). We study three different TSV sizes of $3\mu, 1.5\mu$ and $0.5\mu$ at three diverse technology nodes of 45nm, 32nm and $22\text{nm}$ . These technology variations are considered to investigate the impact on interconnect performance and power in 3D ICs. Our discussion also includes the impact of TSV cluster size variation on TSV capacitance which is important for early performance optimization in any given technology. A delay-aware 3D floorplanning tool with dynamic TSV clustering is used to simultaneously optimize TSV footprint and TSV cluster distribution. Our results show with scaling from 45nm to 22 nm., delay, for all TSV sizes increases by `41 %, while power reduces by `46%.
2 citations
Cites background from "Multi-objective Optimization of Pla..."
...The current TSV-aware approaches predominantly focus on separate minimization of TSVs and wirelength, while ignoring the impact of TSV parasitics [4][6]....
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References
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TL;DR: This paper suggests a non-dominated sorting-based MOEA, called NSGA-II (Non-dominated Sorting Genetic Algorithm II), which alleviates all of the above three difficulties, and modify the definition of dominance in order to solve constrained multi-objective problems efficiently.
Abstract: Multi-objective evolutionary algorithms (MOEAs) that use non-dominated sorting and sharing have been criticized mainly for: (1) their O(MN/sup 3/) computational complexity (where M is the number of objectives and N is the population size); (2) their non-elitism approach; and (3) the need to specify a sharing parameter. In this paper, we suggest a non-dominated sorting-based MOEA, called NSGA-II (Non-dominated Sorting Genetic Algorithm II), which alleviates all of the above three difficulties. Specifically, a fast non-dominated sorting approach with O(MN/sup 2/) computational complexity is presented. Also, a selection operator is presented that creates a mating pool by combining the parent and offspring populations and selecting the best N solutions (with respect to fitness and spread). Simulation results on difficult test problems show that NSGA-II is able, for most problems, to find a much better spread of solutions and better convergence near the true Pareto-optimal front compared to the Pareto-archived evolution strategy and the strength-Pareto evolutionary algorithm - two other elitist MOEAs that pay special attention to creating a diverse Pareto-optimal front. Moreover, we modify the definition of dominance in order to solve constrained multi-objective problems efficiently. Simulation results of the constrained NSGA-II on a number of test problems, including a five-objective, seven-constraint nonlinear problem, are compared with another constrained multi-objective optimizer, and the much better performance of NSGA-II is observed.
37,111 citations
"Multi-objective Optimization of Pla..." refers methods in this paper
...In MO TSV, we have similarity with the framework of Non-dominated Sorting Genetic Algorithm (NSGAII) [12] in the following aspects....
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02 Nov 2009
TL;DR: A new force-directed 3D gate-level placement that efficiently handles TSV usage, and an algorithm that assigns TSVs to nets to complete routing that involves TSVs are presented.
Abstract: Through-Silicon-Via (TSV) is the enabling technology for the fine-grained 3D integration of multiple dies into a single stack. These TSVs occupy non-negligible silicon area because of their sheer size. This significant silicon area occupied by the TSVs and the interconnections made to the TSVs greatly affect area, power, performance, and reliability of 3D IC layouts. Well-managed TSVs alleviate congestion, reduce wirelength, and improve performance, whereas excessive TSVs not only increase the die area, but also have negative impact on many design objectives. In this paper, we study the impact of TSV on various aspects of 3D layouts. We use GDSII layouts of 2D and 3D designs, and thoroughly compare the pros and cons of TSV usage. We propose a new force-directed 3D gate-level placement that efficiently handles TSVs. In addition, we present an algorithm that assigns TSVs to nets to complete routing that involves TSVs. This algorithm, together with our 3D placer, is integrated into a commercial P&R tool to generate fully validated GDSII layouts. Our experiments based on synthesized benchmarks indicate that our algorithms help generate GDSII layouts of 3D designs that are optimized in terms of area, wirelength, and metal layer count.
214 citations
04 Jun 2007
TL;DR: Analytical and partitioning-based techniques are developed to explore the tradeoff between wirelength, interlayer via counts, and thermal effects, which allows wirelengths to be minimized for any desired inter layer via density and temperatures to be reduced while minimizing deleterious effects on wirelength and interlayervia counts.
Abstract: Thermal problems and limitations on interlayer via densities are important design constraints on three-dimensional integrated circuits (3D ICs), and need to be considered during global and detailed placement. Analytical and partitioning-based techniques are developed to explore the tradeoff between wirelength, interlayer via counts, and thermal effects. This method allows wirelengths to be minimized for any desired interlayer via density and temperatures to be reduced while minimizing deleterious effects on wirelength and interlayer via counts. Wirelength reductions within 2% of the optimal can be achieved using 46% fewer interlayer vias. Temperatures can be reduced by about 20% with only 1% higher wirelengths and 10% more interlayer vias.
105 citations
"Multi-objective Optimization of Pla..." refers background in this paper
...In [1], a partitioning-based approach integrates wirelength, temperature, TSV counts, and thermal effect into the min-cut objective....
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...Force-directed 3D placement of cells and TSVs was proposed in [1], [2]....
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TL;DR: An efficient and accurate full-chip thermomechanical stress and reliability analysis tool as well as a design optimization methodology to alleviate mechanical reliability issues in 3D ICs are discussed.
Abstract: Three-dimensional integrated circuit (3D IC) with through-silicon-via (TSV) is believed to offer new levels of efficiency, power, performance, and form-factor advantages over the conventional 2D IC. However, 3D IC involves disruptive manufacturing technologies compared to conventional 2D IC. TSVs cause significant thermomechanical stress that may seriously affect performance, leakage, and reliability of circuits. In this paper, we discuss an efficient and accurate full-chip thermomechanical stress and reliability analysis tool as well as a design optimization methodology to alleviate mechanical reliability issues in 3D ICs. First, we analyze detailed thermomechanical stress induced by TSVs in conjunction with various associated structures such as landing pad and dielectric liner. Then, we explore and validate the linear superposition principle of stress tensors and demonstrate the accuracy of this method against detailed finite element analysis (FEA) simulations. Next, we apply this linear superposition method to full-chip stress simulation and a reliability metric named the von Mises yield criterion. Finally, we propose a design optimization methodology to mitigate the mechanical reliability problems in 3D ICs.
102 citations
"Multi-objective Optimization of Pla..." refers background or methods in this paper
...This is a conservative estimate of dmin based on the TSV size and the technology node [7]....
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...The authors in [7] first analyzed thermomechanical stress and consequent variation in carrier mobility around each TSV and demonstated impact of KOZ on area, wirelength, performance....
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TL;DR: This paper proposes a new 3-D cell placement algorithm that can additionally consider the sizes of TSVs and the physical positions for TSV insertion during placement, and can achieve the best routed wirelength, TSV counts, and total silicon area, in shortest running time.
Abstract: Through-silicon vias (TSVs) are required for transmitting signals among different dies for the 3-D integrated circuit (IC) technology. The significant silicon areas occupied by TSVs bring critical challenges for 3-D IC placement. Unlike most published 3-D placement works that only minimize the number of TSVs during placement due to the limitations in their techniques, this paper proposes a new 3-D cell placement algorithm that can additionally consider the sizes of TSVs and the physical positions for TSV insertion during placement. The algorithm consists of three stages: 1) 3-D analytical global placement with density optimization and whitespace reservation for TSVs; 2) TSV insertion and TSV-aware legalization; and 3) layer-by-layer detailed placement. In particular, the global placement is based on a novel weighted-average (WA) wirelength model, giving the first published model that can outperform the well-known log-sum-exp wirelength model theoretically and empirically. Also, a scheme is proposed to enhance the numerical stability of the WA wirelength model. Furthermore, 3-D routing can easily be accomplished by traditional 2-D routers since the physical positions of TSVs are determined during placement. Experimental results show the effectiveness of our algorithm. Compared with state-of-the-art 3-D cell placement works, our algorithm can achieve the best routed wirelength, TSV counts, and total silicon area, in shortest running time.
64 citations
"Multi-objective Optimization of Pla..." refers background in this paper
...The work in [3] places TSVs in already reserved white-space for TSVs, performs TSV-aware legalization and uses a weighted-average (WA) wirelength model....
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