Proceedings ArticleDOI
Multi-objective Optimization of Placement and Assignment of TSVs in 3D ICs
Debasri Saha,Susmita Sur-Kolay +1 more
- pp 372-377
TLDR
Although this method has some similarity with the framework of NSGA-II, several variations have been incorporated so that, on exploration of variety of non-dominated solutions the search process converges to a near-optimum solution in reasonable time.Abstract:
The advent of 3D IC technology facilitates fabrication of large logic circuits on low area yet high performance chips. For a 3D IC, placement followed by assignment of Through-Silicon-Vias (TSV)s is a challenging problem involving various issues like inter-layer wirelength, power density, congestion and variation in surrounding carrier mobility. Each of the existing techniques for placement of TSVs deals only with a subset of these issues. In this paper, we propose an evolutionary approach MO_TSV to handle this multi-objective optimization problem. Although this method has some similarity with the framework of NSGA-II, several variations have been incorporated so that, on exploration of variety of non-dominated solutions the search process converges to a near-optimum solution in reasonable time. Experimental results on ISCAS'85 and ISCAS'89 benchmarks yield solution quality aswell as convergence times, which are encouraging.read more
Citations
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Journal ArticleDOI
A survey of optimization techniques for thermal-aware 3D processors
TL;DR: This paper shows that the thermal impact on 3D processors is manageable by adopting thermal-aware techniques, thus making3D processors into the mainstream in the near future.
Journal ArticleDOI
Minimizing temperature and energy of real-time applications with precedence constraints on heterogeneous MPSoC systems
TL;DR: The proposed energy/thermal aware task scheduling approach can reduce more temperature by up to about 12∘C (depending on the specific application and related parameters) while keeping a competitive energy consumption compared with the state-of-the-arts.
Journal ArticleDOI
Guided GA-Based Multiobjective Optimization of Placement and Assignment of TSVs in 3-D ICs
Debasri Saha,Susmita Sur-Kolay +1 more
TL;DR: This paper proposes an evolutionary computation approach to handle the problem of placement followed by the assignment of through-silicon vias of 3-D ICs in a novel way so that, on exploration of a variety of nondominated solutions, the search process converges to a near-optimum solution in reasonable time.
Proceedings ArticleDOI
Optimization of Full-Chip Power Distribution Networks in 3D ICs
TL;DR: In this paper, a method to minimize resources of power distribution networks (PDNs) in a three-dimensional integrated circuit (3D IC) under the given design constraints is proposed.
Proceedings ArticleDOI
Through Silicon Via-Aware Layout Design and Power Estimation in Sub-45 Nanometer 3D CMOS IC Technologies
TL;DR: The results show with scaling from 45nm to 22 nm.
References
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Journal ArticleDOI
A fast and elitist multiobjective genetic algorithm: NSGA-II
TL;DR: This paper suggests a non-dominated sorting-based MOEA, called NSGA-II (Non-dominated Sorting Genetic Algorithm II), which alleviates all of the above three difficulties, and modify the definition of dominance in order to solve constrained multi-objective problems efficiently.
Proceedings ArticleDOI
A study of Through-Silicon-Via impact on the 3D stacked IC layout
TL;DR: A new force-directed 3D gate-level placement that efficiently handles TSV usage, and an algorithm that assigns TSVs to nets to complete routing that involves TSVs are presented.
Proceedings ArticleDOI
Placement of 3D ICs with thermal and interlayer via considerations
B. Goplen,Sachin S. Sapatnekar +1 more
TL;DR: Analytical and partitioning-based techniques are developed to explore the tradeoff between wirelength, interlayer via counts, and thermal effects, which allows wirelengths to be minimized for any desired inter layer via density and temperatures to be reduced while minimizing deleterious effects on wirelength and interlayervia counts.
Journal ArticleDOI
TSV stress-aware full-chip mechanical reliability analysis and optimization for 3D IC
TL;DR: An efficient and accurate full-chip thermomechanical stress and reliability analysis tool as well as a design optimization methodology to alleviate mechanical reliability issues in 3D ICs are discussed.
Journal ArticleDOI
TSV-Aware Analytical Placement for 3-D IC Designs Based on a Novel Weighted-Average Wirelength Model
TL;DR: This paper proposes a new 3-D cell placement algorithm that can additionally consider the sizes of TSVs and the physical positions for TSV insertion during placement, and can achieve the best routed wirelength, TSV counts, and total silicon area, in shortest running time.
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Guided GA-Based Multiobjective Optimization of Placement and Assignment of TSVs in 3-D ICs
Debasri Saha,Susmita Sur-Kolay +1 more