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Journal ArticleDOI

Guided GA-Based Multiobjective Optimization of Placement and Assignment of TSVs in 3-D ICs

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TLDR
This paper proposes an evolutionary computation approach to handle the problem of placement followed by the assignment of through-silicon vias of 3-D ICs in a novel way so that, on exploration of a variety of nondominated solutions, the search process converges to a near-optimum solution in reasonable time.
Abstract
The advent of 3-D IC technology facilitates the fabrication of large electronic circuits on small-area chips ensuring high performance. For a 3-D IC, the problem of placement followed by the assignment of through-silicon vias (TSVs) involves optimizing various design objectives such as intertier wirelength, power density, congestion, and separation between the TSVs. Each of the existing techniques for the placement of TSVs deals only with a subset of these objectives. In this paper, we propose an evolutionary computation approach $MO\_{}TSV$ to handle this multiobjective optimization problem. The operators, parameters, and constituents of the framework of genetic algorithm (GA)-based multiobjective optimization have been designed in a novel way so that, on exploration of a variety of nondominated solutions, the search process converges to a near-optimum solution in reasonable time. Experimental results on ISCAS’85, ISCAS’89, ITC’99, and IBM (ISPD’98) benchmarks yield quality solutions in terms of all the parameters as well as convergence times, which are encouraging.

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Citations
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Journal ArticleDOI

An evolutionary approach to implement logic circuits on three dimensional FPGAs

TL;DR: A complete Computer Aided Design (CAD) flow to implement an arbitrary logic circuit on 3D FPGA is proposed and simulation results show more than 60%, 65%, and 23% reduction in TSV count, heat transfer performance, and area respectively, along with 4% increase in critical path delay.
Journal ArticleDOI

Co-Optimization of Test Wrapper Length and TSV for TSV Based 3D SOCs

TL;DR: This work proposes a heuristic procedure to determine the placement of wrapper elements in several layers of 3D SOC for a number of wrapper chains and interconnect them using available number of TSVs such that the length of the longest wrapper length (LWL) is minimized.
Journal ArticleDOI

The Fellini Museum of Rimini in Italy and the Genetic Algorithms-Based Method to Optimize the Design of an Integrated System Network and Installations

Fabio Garzia
- 20 Jun 2022 - 
TL;DR: The Fellini Museum of Rimini is an exhibition hall dedicated to the Rimini film director Federico Fellini, included by the Ministry of Culture of Italy among the great national cultural projects as mentioned in this paper .
Book ChapterDOI

Fundamentals of Heat Dissipation in 3D IC Packaging and Thermal-Aware Design

TL;DR: An overview of the available cooling options for 3D ICs and their performance evaluation are presented in this paper, along with an overview of interlayer cooling with microchannels and introducing fins in the coolant flow paths.
Proceedings ArticleDOI

Particle Swarm Optimization and Genetic Algorithms for PID Controller Tuning

TL;DR: In this article , the tuning of an inverted pendulum's proportional-integral-derivative (PID) parameters using heuristic approaches is compared. But the tuning process is subsequently turned into an optimization issue and a mix of particle swarm optimization and genetic algorithms are used to overcome this issue.
References
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Journal ArticleDOI

A fast and elitist multiobjective genetic algorithm: NSGA-II

TL;DR: This paper suggests a non-dominated sorting-based MOEA, called NSGA-II (Non-dominated Sorting Genetic Algorithm II), which alleviates all of the above three difficulties, and modify the definition of dominance in order to solve constrained multi-objective problems efficiently.
Book

Space-filling curves

Hans Sagan
TL;DR: The subject of space-filling curves has generated a great deal of interest in the 100 years since the first such curve was discovered by Peano as discussed by the authors, but there have been no comprehensive treatment of the subject since Siepinsky's in 1912.
Proceedings ArticleDOI

A study of Through-Silicon-Via impact on the 3D stacked IC layout

TL;DR: A new force-directed 3D gate-level placement that efficiently handles TSV usage, and an algorithm that assigns TSVs to nets to complete routing that involves TSVs are presented.
Proceedings ArticleDOI

Placement of 3D ICs with thermal and interlayer via considerations

TL;DR: Analytical and partitioning-based techniques are developed to explore the tradeoff between wirelength, interlayer via counts, and thermal effects, which allows wirelengths to be minimized for any desired inter layer via density and temperatures to be reduced while minimizing deleterious effects on wirelength and interlayervia counts.
Journal ArticleDOI

TSV stress-aware full-chip mechanical reliability analysis and optimization for 3D IC

TL;DR: An efficient and accurate full-chip thermomechanical stress and reliability analysis tool as well as a design optimization methodology to alleviate mechanical reliability issues in 3D ICs are discussed.
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