Guided GA-Based Multiobjective Optimization of Placement and Assignment of TSVs in 3-D ICs

Abstract: In 3D IC, wrapper chains can span across vertical directions which causes the increase in number of TSVs(through-silicon-vias)(which is used to interconnect different cores in the vertical directions). Excessive use of TSVs in wrapper design causes routing congestion and additional overhead in manufacturing. Therefore, optimization of wrapper length and judicious use of TSVs are the focus of 3D wrapper architecture design. In this work, we first propose a heuristic procedure to determine the placement of wrapper elements in several layers of 3D SOC for a number of wrapper chains and interconnect them using available number of TSVs such that the length of the longest wrapper length (LWL) is minimized. Then we apply particle swarm optimization (PSO) based metaheuristic approach on the results obtained in first case to determine the placement of wrapper chains and interconnect them using minimum number of TSVs such that the length of LWL is minimized. We compare our results with earlier works and the experimental results show the efficacy of our algorithm.

Abstract: Cooling of a planar 2D IC chip utilizes heat transfer from a face of the chip though a heat sink. In case of a 3D IC chip stack, the individual chip faces are not available for mounting conventional heat sinks. Mounting the heat sinks on the ends is feasible, but the heat flow paths for the interior chips from the junction to the heat sink become longer. Further, multiple heat sources present along the heat flow paths in stacked chips may create localized hot spots which exceed the allowable junction temperatures. While 2.5D integration in complex ICs where individual layers are mounted on another base die called an interposer can alleviate the heat dissipation issues, it cannot deliver the benefits of monolithic 3D ICs due to the planar distance between the chips or chiplets over the interposer. Introducing interlayer cooling with microchannels and introducing fins in the coolant flow paths extend the thermal dissipation capability of a 3D stack; however this is often accompanied with taller microchannels that lead to longer lengths of through-silicon-vias (TSVs). Placement of TSVs, microchannels walls and fins present conflicting design requirements. Therefore co-design and innovative approaches are seen as critical before widespread commercialization of 3D ICs becomes a reality. An overview of the available cooling options for 3D ICs and their performance evaluation are presented in this chapter.

Abstract: Three Dimensional Field Programmable Gate Arrays (3D FPGAs) recently are presented as the next generation of the FPGA family to continue the integration of more transistors on a single chip seamlessly. The 3D FPGA are fabricated by stacking several layers of semiconductor substrates and the interconnection among layers are realized using Through Silicon Vias (TSVs). Despite their benefits regarding less area and higher speed, 3D FPGAs encounter two major problems; huge size of single TSV and trapping generated heat in inner layers. To handle these problems, we propose a complete Computer Aided Design (CAD) flow to implement an arbitrary logic circuit on 3D FPGA. Prtitioning, Placement, and Routing are primary stages of the proposed CAD flow. The partitioning and placement stages of the flow are based on Simulated Annealing algorithm. Furthermore, the routing stage is a modified version of the Pathfinder algorithm. Unbalanced SA based partitioning tremendously reduces the required TSVs along with distribution of highly active circuit’s modules on the bottom layers and constructing thermal channels facilitate transferring the generated heat in intermediate layers. Simulation results show more than 60%, 65%, and 23% reduction in TSV count, heat transfer performance, and area respectively, along with 4% increase in critical path delay. In addition, comparison between 2D FPGA and 3D FPGA with our proposed architecture (including 2 tier), shows that the circuit speed increases by 28.61%, and minimum channel width decreases by 30.47%. Finally, the results of comparison between 2-tier and 4-tier in 3D FPGA show that circuit speed and minimum channel width increase by 15.95% and 15.92% in 4-tier, respectively.

Abstract: Multi-objective evolutionary algorithms (MOEAs) that use non-dominated sorting and sharing have been criticized mainly for: (1) their O(MN/sup 3/) computational complexity (where M is the number of objectives and N is the population size); (2) their non-elitism approach; and (3) the need to specify a sharing parameter. In this paper, we suggest a non-dominated sorting-based MOEA, called NSGA-II (Non-dominated Sorting Genetic Algorithm II), which alleviates all of the above three difficulties. Specifically, a fast non-dominated sorting approach with O(MN/sup 2/) computational complexity is presented. Also, a selection operator is presented that creates a mating pool by combining the parent and offspring populations and selecting the best N solutions (with respect to fitness and spread). Simulation results on difficult test problems show that NSGA-II is able, for most problems, to find a much better spread of solutions and better convergence near the true Pareto-optimal front compared to the Pareto-archived evolution strategy and the strength-Pareto evolutionary algorithm - two other elitist MOEAs that pay special attention to creating a diverse Pareto-optimal front. Moreover, we modify the definition of dominance in order to solve constrained multi-objective problems efficiently. Simulation results of the constrained NSGA-II on a number of test problems, including a five-objective, seven-constraint nonlinear problem, are compared with another constrained multi-objective optimizer, and the much better performance of NSGA-II is observed.

Abstract: The subject of space-filling curves has generated a great deal of interest in the 100 years since the first such curve was discovered by Peano. Cantor, Hilbert, Moore, Knopp, Lebesgue and Polya are among the prominent mathematicians who have contributed to the field. However, there have been no comprehensive treatment of the subject since Siepinsky's in 1912. Cantor showed in 1878 that the number of points on an interval is the same as the number of points in a square, while in 1890 Peano showed that there is indeed a continuous curve that maps all points of a line onto all points of a square, although the curve exists only as a limit of very convoluted curves. This book discusses generalizations of Peano's solution and the properties that such curves must possess. It also discusses fractals in this context.

Abstract: Through-Silicon-Via (TSV) is the enabling technology for the fine-grained 3D integration of multiple dies into a single stack. These TSVs occupy non-negligible silicon area because of their sheer size. This significant silicon area occupied by the TSVs and the interconnections made to the TSVs greatly affect area, power, performance, and reliability of 3D IC layouts. Well-managed TSVs alleviate congestion, reduce wirelength, and improve performance, whereas excessive TSVs not only increase the die area, but also have negative impact on many design objectives. In this paper, we study the impact of TSV on various aspects of 3D layouts. We use GDSII layouts of 2D and 3D designs, and thoroughly compare the pros and cons of TSV usage. We propose a new force-directed 3D gate-level placement that efficiently handles TSVs. In addition, we present an algorithm that assigns TSVs to nets to complete routing that involves TSVs. This algorithm, together with our 3D placer, is integrated into a commercial P&R tool to generate fully validated GDSII layouts. Our experiments based on synthesized benchmarks indicate that our algorithms help generate GDSII layouts of 3D designs that are optimized in terms of area, wirelength, and metal layer count.

Abstract: Thermal problems and limitations on interlayer via densities are important design constraints on three-dimensional integrated circuits (3D ICs), and need to be considered during global and detailed placement. Analytical and partitioning-based techniques are developed to explore the tradeoff between wirelength, interlayer via counts, and thermal effects. This method allows wirelengths to be minimized for any desired interlayer via density and temperatures to be reduced while minimizing deleterious effects on wirelength and interlayer via counts. Wirelength reductions within 2% of the optimal can be achieved using 46% fewer interlayer vias. Temperatures can be reduced by about 20% with only 1% higher wirelengths and 10% more interlayer vias.

Abstract: Three-dimensional integrated circuit (3D IC) with through-silicon-via (TSV) is believed to offer new levels of efficiency, power, performance, and form-factor advantages over the conventional 2D IC. However, 3D IC involves disruptive manufacturing technologies compared to conventional 2D IC. TSVs cause significant thermomechanical stress that may seriously affect performance, leakage, and reliability of circuits. In this paper, we discuss an efficient and accurate full-chip thermomechanical stress and reliability analysis tool as well as a design optimization methodology to alleviate mechanical reliability issues in 3D ICs. First, we analyze detailed thermomechanical stress induced by TSVs in conjunction with various associated structures such as landing pad and dielectric liner. Then, we explore and validate the linear superposition principle of stress tensors and demonstrate the accuracy of this method against detailed finite element analysis (FEA) simulations. Next, we apply this linear superposition method to full-chip stress simulation and a reliability metric named the von Mises yield criterion. Finally, we propose a design optimization methodology to mitigate the mechanical reliability problems in 3D ICs.