Journal ArticleDOI
Niagara: a 32-way multithreaded Sparc processor
Reads0
Chats0
TLDR
The Niagara processor implements a thread-rich architecture designed to provide a high-performance solution for commercial server applications that exploits the thread-level parallelism inherent to server applications, while targeting low levels of power consumption.Abstract:
The Niagara processor implements a thread-rich architecture designed to provide a high-performance solution for commercial server applications. This is an entirely new implementation of the Sparc V9 architectural specification, which exploits large amounts of on-chip parallelism to provide high throughput. The hardware supports 32 threads with a memory subsystem consisting of an on-board crossbar, level-2 cache, and memory controllers for a highly integrated design that exploits the thread-level parallelism inherent to server applications, while targeting low levels of power consumption.read more
Citations
More filters
Proceedings ArticleDOI
McPAT: an integrated power, area, and timing modeling framework for multicore and manycore architectures
TL;DR: Combining power, area, and timing results of McPAT with performance simulation of PARSEC benchmarks at the 22nm technology node for both common in-order and out-of-order manycore designs shows that when die cost is not taken into account clustering 8 cores together gives the best energy-delay product, whereas when cost is taking into account configuring clusters with 4 cores gives thebest EDA2P and EDAP.
Proceedings ArticleDOI
Evaluating MapReduce for Multi-core and Multiprocessor Systems
TL;DR: It is established that, given a careful implementation, MapReduce is a promising model for scalable performance on shared-memory systems with simple parallel code.
Proceedings ArticleDOI
The multikernel: a new OS architecture for scalable multicore systems
Andrew Baumann,Paul Barham,Pierre-Évariste Dagand,Tim Harris,Rebecca Isaacs,Simon Peter,Timothy Roscoe,Adrian Schüpbach,Akhilesh Singhania +8 more
TL;DR: This work investigates a new OS structure, the multikernel, that treats the machine as a network of independent cores, assumes no inter-core sharing at the lowest level, and moves traditional OS functionality to a distributed system of processes that communicate via message-passing.
Journal ArticleDOI
Photonic Networks-on-Chip for Future Generations of Chip Multiprocessors
TL;DR: Results confirm the unique benefits for future generations of CMPs that can be achieved by bringing optics into the chip in the form of photonic NoCs, as well as a comparative power analysis of a photonic versus an electronic NoC.
Proceedings ArticleDOI
ORION 2.0: a fast and accurate NoC power and area model for early-stage design space exploration
TL;DR: The development of ORION 2.0, an extensive enhancement of the original ORION models which includes completely new subcomponent power models, area models, as well as improved and updated technology models, confirms the need for accurate early-stage NoC power estimation.
References
More filters
Journal ArticleDOI
Web search for a planet: The Google cluster architecture
TL;DR: Googless architecture features clusters of more than 15,000 commodity-class PCs with fault tolerant software that achieves superior performance at a fraction of the cost of a system built from fewer, but more expensive, high-end servers.
Proceedings ArticleDOI
The case for a single-chip multiprocessor
TL;DR: It is shown that in advanced technologies it is possible to implement a single-chip multiprocessor in the same area as a wide issue superscalar processor, and it is found that for applications with little parallelism the performance of the two microarchitectures is comparable.
Proceedings ArticleDOI
Piranha: a scalable architecture based on single-chip multiprocessing
Luiz Andre Barroso,Kourosh Gharachorloo,Robert McNamara,Andreas Nowatzyk,Shaz Qadeer,Barton Sano,Scott Smith,Robert J. Stets,Ben Verghese +8 more
TL;DR: The Piranha system, a research prototype being developed at Compaq that aggressively exploits chip multiprocessing by integrating eight simple Alpha processor cores along with a two-level cache hierarchy onto a single chip, is described.
Proceedings ArticleDOI
Interleaving: a multithreading technique targeting multiprocessors and workstations
TL;DR: It is shown that while current multiple-context designs work reasonably well for multiprocessors, they are ineffective in hiding the much shorter uniprocessor latencies using the limited parallelism found in workstation environments, and an alternative design is proposed that combines the best features of two existing approaches.
Proceedings ArticleDOI
A Power-Efficient High-Throughput 32-Thread SPARC Processor
Ana Sonia Leon,Jinuk Luke Shin,K.W. Tam,W. Bryg,Francis Schumacher,P. Kongetira,D. Weisner,A. Strong +7 more
TL;DR: The first generation of Niagara SPARC processors implements a power-efficient multi-threading architecture to achieve high throughput with minimum hardware complexity.