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Proceedings ArticleDOI

Non-tree routing

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TLDR
It is shown that adding extra wires to an existing routing tree can often significantly improve signal propagation delay by exploiting a tradeoff between wire capacitance and resistance, and a new routing algorithm is proposed based on this phenomenon.
Abstract
An implicit premise of existing routing methods is that the routing topology must correspond to a tree (ie it does not contain cycles) In this paper we investigate the consequences of abandoning this basic axiom, and instead allow routing topologies that correspond to arbitrary graphs (ie where cycles are admissible) We show that adding extra wires to an existing routing tree can often significantly improve signal propagation delay by exploiting a tradeoff between wire capacitance and resistance, and we propose a new routing algorithm based on this phenomenon Using SPICE to determine the efficacy of our methods, we obtain dramatic results: for example, the judicious addition of a few extra wires to an existing Steiner routing reduces the signal propagation delay by an average of up to 62%, with relatively modest total wirelength increase, depending on net size and the technology parameters Finally, we observe that non-tree routing also significantly reduces signal skew >

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Citations
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Journal ArticleDOI

Optimal wiresizing for interconnects with multiple sources

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Proceedings ArticleDOI

Non-tree routing for reliability and yield improvement

TL;DR: A postprocessing, tree-augmentation approach to introduce redundant interconnects for manufacturing yield and reliability improvement and gives a comprehensive experimental study comparing the solution quality and runtime of the methods with the best methods reported in the literature.
Proceedings ArticleDOI

Comprehensive frequency-dependent substrate noise analysis using boundary element methods

TL;DR: In this article, a new and efficient method is introduced for the calculation of the Green's function that can accommodate arbitrary substrate doping profiles and thus facilitate substrate noise analysis using boundary element methods.
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Yield Improvement by Local Wiring Redundancy

TL;DR: This paper describes a technique that improves yield by adding via redundancy through the use of local loops, which reduces critical area, does not require wrong-way wiring, and achieves a higher percent of redundant vias.
Proceedings ArticleDOI

Research directions for coevolution of rules and routers

TL;DR: In this paper, the authors review types and causes of "difficult" design rules, as well as implications for current routing approaches, and assess some basic router components with respect to future viability.
References
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The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers

TL;DR: It is found possible to define delay time and rise time in such a way that these quantities can be computed very simply from the Laplace system function of the network.
Journal ArticleDOI

Signal Delay in RC Tree Networks

TL;DR: Upper and lower bounds for delay that are computationally simple are presented in this paper and can be used to bound the delay, given the signal threshold, and to certify that a circuit is "fast enough," given both the maximum delay and the voltage threshold.
Journal ArticleDOI

Computer-aided design

TL;DR: This project is engaged in a program of research into the application of the concepts and techniques of modern data processing to the design of mechanical parts and the further development of automatic programming systems for numerically controlled machine tools.
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