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Proceedings ArticleDOI: 10.1109/ISCO.2015.7282231

Novel Vedic mathematics based ALU using application specific reversibility

01 Oct 2015-pp 1-5
Abstract: The proposed project utilizes the computational speed advantages of Vedic algorithm and energy optimization benefits of Reversible circuit. The Vedic algorithm optimizes the conventional mathematic computation logic used in the current processors thereby, effectively increasing the speed of computation. The Urdhva Triyambakam method derived from the ancient Indian mathematics will be used in the proposed project. Reversible circuits, on the other hand, reduces the power dissipation incurred due information/bits loss as in the case of an irreversible circuit making way for better power utilization along with reduced heat dissipation. The proposed project introduces the concept of application specific reversibility wherein the logical states belonging only to a particular function of the module is being considered, which significantly impacts in reducing the area limitations of a reversible unit while keeping its power efficiency benefits. The circuit design presented utilizes the above technique mentioned while designing the adder, multiplier along with other modules of an ALU.

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Topics: Adder (53%), Circuit design (52%), Logic gate (51%)
Citations
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Proceedings ArticleDOI: 10.1109/ICRAECC43874.2019.8995165
07 Mar 2019-
Abstract: There is an ever increasing demand for low-power and high-speed designs due to the emergence of portable, handheld gadgets which run on batteries. More and more research works in VLSI are concentrated on different methodologies to reduce the power consumption of a system and also increase its throughput. Multiplication is an important operation in almost all computations. Design of multipliers with low power utilization and increased throughput will lead to systems with reduced power usage and high speed. Vedic Multipliers based on the Urdhava Tiryakbhyam sutra delivers results faster than the customary methods. Reversible logic gates when used in a circuit lead to little or no power dissipation. The paper proposes a system which employs Vedic multipliers and reversible gates to perform multiplications with increased throughput and using very little power. The designed system is optimized by combining the low power strategy of reversible logic and the high speed calculation of Urdhava Tiryakbhyam Vedic multiplier.

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Topics: Logic gate (53%), Very-large-scale integration (51%), Toffoli gate (50%)

2 Citations


Proceedings ArticleDOI: 10.1109/RTEICT.2017.8256743
01 May 2017-
Abstract: Electronics, and in particular the integrated circuits has been made possible the design of powerful and flexible processors. Having this vision in mind, a dedicated architecture is proposed in this paper which is exclusively used for multiplication of two numbers based on the Vedic sutras. The most significant operation in any signal processing and scientific applications is multiplication. The use of squaring circuits in place of general multipliers can reduce the number of inputs and thereby significantly will reduce the area consumed. To accomplish this, we have implemented Nikhilam Sutra, which is one of the sixteen sutras in Vedic Mathematics. This is dedicated for computing the square of the number. This technique is further extended for finding the product of the binary numbers. The performance for the proposed design is compared with the existing multipliers, on the basis of delay and area utilization. The results prove that the architecture prosed using Nikhilam sutra improves the efficiency considerably. The design has been implemented using Verilog HDL for 8 bit numbers and the synthesis is done using Xilinx ISE 14.5 software.

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Topics: Binary multiplier (55%), Multiplication (55%), Verilog (54%)

2 Citations


Book ChapterDOI: 10.1007/978-981-15-5558-9_61
Dhanunjay Lachireddy1, S. R. Ramesh1Institutions (1)
01 Jan 2020-
Abstract: The power consumption and speed of a device is a crucial factor as most of the designs move towards the system-in-package and system-on-chip products. As the size of the device scale down, speed and power consumption doesn’t go hand in hand. Switching power in a CMOS circuit is a prime component of the total power consumption. This switching power is caused by simultaneous charging and discharging of the load capacitances when the signal undergoes transition. The speed of a digital circuit is determined by how fast the circuit can generate outputs from the given inputs. There are various ways to reduce power consumption such as voltage scaling, clock gating, reversible logic, and so on. For increasing the speed of a circuit, delay inside the logic should be reduced. The choice of a smarter design architecture helps in improving the circuit speed. This work focuses on an ALU design using Vedic algorithm and reversible logic. It aims for better speed and power. The proposed Vedic algorithm based ALU design yields 6.7% decrease in dynamic power and 2.2% decrease in a number of cells used.

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Topics: Clock gating (60%), Dynamic demand (58%), Digital electronics (54%) ...read more

2 Citations


Proceedings ArticleDOI: 10.1109/RTEICT42901.2018.9012469
S Nithyashree1, Y ChanduInstitutions (1)
18 May 2018-
Abstract: High speed and less area have always been a major concern in VLSI design. With this as a constraint, in this paper a dedicated architecture which is exclusively used for squaring operation has been proposed. Squaring plays a vital role in many signal processing applications and probabilistic analysis in communication systems, where, quite often general multipliers are used although squaring has to be done. This unnecessarily increases the area of the design and also increases the computation time. The principles of Nikhilam Sutra have been leveraged and is extended for squaring binary bits. A comparative study of the projected architecture and the prevailing multipliers, on the premise of delay and space utilization is presented. The simulation outcome proves that the design projected employing Nikhilam sutra improves the performance significantly. The 8-bit architecture has been developed by Verilog HDL and the synthesis is completed using Xilinx ISE - 14.5 software.

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Topics: Verilog (51%)
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Journal ArticleDOI: 10.1147/RD.441.0261
Abstract: It is argued that computing machines inevitably involve devices which perform logical functions that do not have a single-valued inverse. This logical irreversibility is associated with physical irreversibility and requires a minimal heat generation, per machine cycle, typically of the order of kT for each irreversible function. This dissipation serves the purpose of standardizing signals and making them independent of their exact logical history. Two simple, but representative, models of bistable devices are subjected to a more detailed analysis of switching kinetics to yield the relationship between speed and energy dissipation, and to estimate the effects of errors induced by thermal fluctuations.

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Topics: Heat generation (58%), Dissipation (52%), Reversible computing (51%)

3,308 Citations


Open accessJournal Article
01 Feb 2005-IEEE Potentials
Abstract: This work presents the logical reversibility. The inputs and outputs of reversible logic gates can be uniquely retrievable from each other. The reversible logic operations can't erase information and dissipate zero heat. The circuit actually operates in a backward operation, allows reproducing the inputs from the outputs and consumes zero power. As the basic elements of any logic circuit, logic gates are used to realize Boolean functions. By combining reversible logic gates, reversible circuits can perform complex logical and arithmetic operations. A one-to-one mapping between inputs and outputs is realized. The logical operations run backwards by cascading a reversible logic gate with its dual (inverse). Reversible circuits are also called lossless circuits, as there is neither energy loss nor information loss. These circuits are very attractive for applications where extremely low power consumption, or heat dissipation, is desirable in areas ranging from communications, low power VLSI (very large-scale integration) technology, optical computing to nanotechnology. Reversible logic found to be very useful in quantum computing where the quantum evolution is inherently reversible.

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Topics: Three-input universal logic gate (68%), Logic family (67%), Reversible computing (67%) ...read more

109 Citations


Proceedings ArticleDOI: 10.1109/ISVLSI.2011.30
04 Jul 2011-
Abstract: Reversible logic is widely being considered as the potential logic design style for implementation in modern nanotechnology and quantum computing with minimal impact on physical entropy. Recent advances in reversible logic allow for improved quantum computer algorithms and schemes for corresponding computer architectures. Significant contributions have been made in the literature towards the design of reversible logic gate structures and arithmetic units, however, there are not many efforts directed towards the design of reversible ALUs. In this paper, we propose the design of two programmable reversible logic gate structures targeted at ALU implementation and their use in the realization of an efficient reversible ALU is demonstrated. The proposed ALU design is verified and its advantages over the only existing ALU design are quantitatively analyzed.

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Topics: Logic synthesis (60%), Logic gate (60%), Arithmetic logic unit (56%)

89 Citations


Open accessPosted Content
Abstract: In the recent years, reversible logic has emerged as a promising technology having its applications in low power CMOS, quantum computing, nanotechnology, and optical computing. The classical set of gates such as AND, OR, and EXOR are not reversible. This paper proposes a new 4 * 4 reversible gate called TSG gate. The proposed gate is used to design efficient adder units. The most significant aspect of the proposed gate is that it can work singly as a reversible full adder i.e reversible full adder can now be implemented with a single gate only. The proposed gate is then used to design reversible ripple carry and carry skip adders. It is demonstrated that the adder architectures designed using the proposed gate are much better and optimized, compared to their existing counterparts in literature; in terms of number of reversible gates and garbage outputs. Thus, this paper provides the initial threshold to building of more complex system which can execute more complicated operations using reversible logic.

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Topics: Adder (72%), Toffoli gate (67%), NAND gate (65%) ...read more

47 Citations


Proceedings ArticleDOI: 10.1109/ICCPCT.2013.6528848
T. R. Rakshith1, Rakshith Saligram2Institutions (2)
20 Mar 2013-
Abstract: Multipliers are vital components of any processor or computing machine. More often than not, performance of microcontrollers and Digital signal processors are evaluated on the basis of number of multiplications performed in unit time. Hence better multiplier architectures are bound to increase the efficiency of the system. Vedic multiplier is one such promising solution. Its simple architecture coupled with increased speed forms an unparalleled combination for serving any complex multiplication computations. Tagged with these highlights, implementing this with reversible logic further reduces power dissipation. Power dissipation is another important constraint in an embedded system which cannot be neglected. In this paper we bring out a Vedic multiplier known as “Urdhva Tiryakbhayam” meaning vertical and crosswise, implemented using reversible logic, which is the first of its kind. This multiplier may find applications in Fast Fourier Transforms (FFTs), and other applications of DSP like imaging, software defined radios, wireless communications.

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41 Citations


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