Proceedings ArticleDOI
On multiple bridging faults
Irith Pomeranz,Sudhakar M. Reddy +1 more
- pp 221-226
TLDR
It is shown that fault activation conditions are more difficult to create for certain multiple faults than for the single faults that comprise them, and a test set for single bridging faults may leave significant percentages of detectable multiple faults undetected.Abstract:
Multiple faults are typically detected by test sets for single faults. For bridging faults, we show that fault activation conditions are more difficult to create for certain multiple faults than for the single faults that comprise them. As a result, a test set for single bridging faults may leave significant percentages of detectable multiple faults undetected. We discuss three such cases, corresponding to three types of bridging faults, and present experimental results for one of them. As part of this study we consider the ability of a 10-detection test set for single stuck-at faults to detect multiple bridging faults of this type.read more
Citations
More filters
Journal ArticleDOI
Layout Resynthesis by Applying Design-for-manufacturability Guidelines to Avoid Low-coverage Areas of a Cell-based Design
TL;DR: This article uses a resynthesis procedure to target areas of the design where large numbers of external faults related to DFM guideline violations are undetectable, and ensures that the circuit does not suffer from low-coverage areas that may result in detectable systematic defects escaping detection, but failing the circuit in the field.
Proceedings ArticleDOI
Selecting target bridging faults for uniform circuit coverage
TL;DR: A procedure for the selection of subsets of bridging faults that addresses the need to provide a uniform coverage of the circuit in order to prevent areas with low coverage from resulting in test escapes is developed.
Book ChapterDOI
Switch Line Fault Diagnosis in FPGA Interconnects Using Line Tracing Approach
Shilpa Dandoti,V. D. Mytri +1 more
TL;DR: The testing of interconnect types like single lines, double lines, global interconnect, Long length lines, switching matrices, Buffer drivers, Quad lines and direct lines, using a test manager which defines a part of the chip as the pattern generator and the other half as response analyzer is discussed.
References
More filters
Book
Digital Systems Testing and Testable Design
TL;DR: The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.
Journal ArticleDOI
A method of fault analysis for test generation and fault diagnosis
H. Cox,Janusz Rajski +1 more
TL;DR: The authors present a fault coverage analysis method for test generation and fault diagnosis of large combinational circuits using a 16-valued logic system, GEMINI, and an extended fault model which includes stuck-at, stuck-open, and delay faults is used.
Proceedings ArticleDOI
Biased voting: A method for simulating CMOS bridging faults in the presence of variable gate logic thresholds
TL;DR: A general technique which can be used to determine if a particular structure of transistors gives rise to a bridge voltage which is higher or lower than a given threshold, in most cases without requiring circuit simulation.
Journal ArticleDOI
Multiple Fault Diagnosis in Combinational Circuits Based on an Effect-Cause Analysis
Abramovici,Breuer +1 more
TL;DR: The main vehicle of this approach is the deduction of internal line values in a circuit under test N*.
Proceedings ArticleDOI
Resistive bridge fault modeling, simulation and test generation
V.R. Sar-Dessai,Duncan M. Walker +1 more
TL;DR: In this article, the authors developed a model of resistive bridging faults and studied the fault coverage on ISCAS85 circuits of different test sets using resistive and zero-ohm bridges at different supply voltages.
Related Papers (5)
Using dummy bridging faults to define a reduced set of target faults
Irith Pomeranz,Sudhakar M. Reddy +1 more