Journal ArticleDOI
On routability for FPGAs under faulty conditions
Kaushik Roy,S. Nag +1 more
TLDR
The PI faults are model and the design and routability of the FPGA channel architecture is addressed to achieve 100% routing with minimum performance penalty in the presence of PI faults to show the feasibility of achieving routability with minimumperformance penalty when a large number of faults are present in the channel.Abstract:Â
The field programmable gate array (FPGA) routing resources are fixed and their usage is constrained by the location of programmable interconnects (PIs) such as antifuses. The routing or the interconnect delays are determined by the length of segments assigned to the nets of various lengths and the number of PIs programmed for routing of each net. Due to the use of PIs certain unconventional faults may appear. In this paper we model the PI faults and address the design and routability of the FPGA channel architecture to achieve 100% routing with minimum performance penalty in the presence of PI faults. A channel routing algorithm has also been developed which routes nets in the presence of PI faults. Experiments were performed by randomly injecting faults of different types into the routing channel and then using the routing algorithm to determine the routability of the synthesized architecture. Results on a set of industrial designs and MCNC benchmark examples show the feasibility of achieving routability with minimum performance penalty when a large number of faults are present in the channel. >read more
Citations
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Proceedings ArticleDOI
Using roving STARs for on-line testing and diagnosis of FPGAs in fault-tolerant applications
TL;DR: A new fault-tolerant (FT) technique allows using partially defective FPGA resources for normal operation, providing longer mission life-span in the presence of faults, and the basic concepts of a new dynamic FT method are introduced.
Journal ArticleDOI
Methodologies for tolerating cell and interconnect faults in FPGAs
F. Hanchek,Shantanu Dutt +1 more
TL;DR: Compared to other techniques for fault tolerance in FPGAs, these methods are shown to provide significantly greater yield improvement, and a 35 percent non-FT chip yield for a 16/spl times/16 FPGA is more than doubled.
Proceedings ArticleDOI
BIST-based diagnostics of FPGA logic blocks
TL;DR: This paper presents the first approach able to diagnose faulty programmable logic blocks (PLBs) in Field Programmable Gate Arrays (FPGAs) with maximal diagnostic resolution, based on a new Built-In Self-Test (BIST) architecture for FPGAs and can accurately locate any single and most multiple faulty PLBs.
Proceedings ArticleDOI
Roving STARs: an integrated approach to on-line testing, diagnosis, and fault tolerance for FPGAs in adaptive computing systems
TL;DR: This work presents an integrated approach to on-line FPGA testing, diagnosis and fault tolerance, to be used in high-reliability and high-availability hardware and ensures that spare resources are always present in the neighborhood of the located fault, thus simplifying fault-bypassing.
Journal ArticleDOI
On-line fault detection for bus-based field programmable gate arrays
TL;DR: A technique for on-line built-in self-testing of bus-based field programmable gate arrays (FPGAs) without using special-purpose hardware, hardware external to the device, and without interrupting system operation is introduced.
References
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Proceedings ArticleDOI
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Rajeev Murgai,Yoshihito Nishizaki,Narendra Shenoy,Robert K. Brayton,Alberto Sangiovanni-Vincentelli +4 more
TL;DR: The problem of combinational logic synthesis is addressed for two interesting and popular classes of programmable gate array architectures: table-look-up and multiplexor-based.
Proceedings ArticleDOI
Chortle: a technology mapping program for lookup table-based field programmable gate arrays
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